202 lines
4.7 KiB
C
202 lines
4.7 KiB
C
/** @file
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C based implemention of IA32 interrupt handling only
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requiring a minimal assembly interrupt entry point.
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Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuDxe.h"
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//
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// Local structure definitions
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//
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#pragma pack (1)
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//
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// Global Descriptor Entry structures
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//
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typedef struct _GDT_ENTRY {
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UINT16 Limit15_0;
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UINT16 Base15_0;
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UINT8 Base23_16;
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UINT8 Type;
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UINT8 Limit19_16_and_flags;
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UINT8 Base31_24;
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} GDT_ENTRY;
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typedef
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struct _GDT_ENTRIES {
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GDT_ENTRY Null;
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GDT_ENTRY Linear;
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GDT_ENTRY LinearCode;
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GDT_ENTRY SysData;
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GDT_ENTRY SysCode;
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GDT_ENTRY LinearCode64;
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GDT_ENTRY Spare4;
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GDT_ENTRY Spare5;
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} GDT_ENTRIES;
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#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)
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#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)
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#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)
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#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)
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#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)
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#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
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#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)
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#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)
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#if defined (MDE_CPU_IA32)
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#define CPU_CODE_SEL LINEAR_CODE_SEL
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#define CPU_DATA_SEL LINEAR_SEL
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#elif defined (MDE_CPU_X64)
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#define CPU_CODE_SEL LINEAR_CODE64_SEL
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#define CPU_DATA_SEL LINEAR_SEL
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//#else
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//#error CPU type not supported for CPU GDT initialization!
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#endif
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//
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// Global descriptor table (GDT) Template
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//
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STATIC GDT_ENTRIES GdtTemplate = {
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//
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// NULL_SEL
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//
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{
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0x0, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x0, // type
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0x0, // limit 19:16, flags
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0x0, // base 31:24
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},
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//
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// LINEAR_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x092, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// LINEAR_CODE_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x09A, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_DATA_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x092, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_CODE_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x09A, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// LINEAR_CODE64_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x09B, // present, ring 0, code, expand-up, writable
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0x0AF, // LimitHigh (CS.L=1, CS.D=0)
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0x0, // base (high)
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},
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//
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// SPARE4_SEL
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//
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{
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0x0, // limit 0
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0x0, // base 0
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0x0,
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0x0, // present, ring 0, data, expand-up, writable
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0x0, // page-granular, 32-bit
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0x0,
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},
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//
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// SPARE5_SEL
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//
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{
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0x0, // limit 0
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0x0, // base 0
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0x0,
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0x0, // present, ring 0, data, expand-up, writable
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0x0, // page-granular, 32-bit
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0x0,
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},
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};
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/**
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Initialize Global Descriptor Table.
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**/
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VOID
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InitGlobalDescriptorTable (
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VOID
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)
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{
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GDT_ENTRIES *gdt;
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IA32_DESCRIPTOR gdtPtr;
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//
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// Allocate Runtime Data for the GDT
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//
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gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
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ASSERT (gdt != NULL);
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gdt = ALIGN_POINTER (gdt, 8);
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//
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// Initialize all GDT entries
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//
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CopyMem(gdt, &GdtTemplate, sizeof (GdtTemplate));
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//
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// Write GDT register
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//
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//gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
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gdtPtr.Base = (UINTN)(VOID*) gdt;
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gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
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AsmWriteGdtr (&gdtPtr);
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//
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// Update selector (segment) registers base on new GDT
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//
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SetCodeSelector ((UINT16)CPU_CODE_SEL);
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SetDataSelectors ((UINT16)CPU_DATA_SEL);
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}
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