791 lines
24 KiB
C
791 lines
24 KiB
C
/** @file
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MSR Definitions for the Intel(R) Atom(TM) Processor Family.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.
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**/
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#ifndef __ATOM_MSR_H__
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#define __ATOM_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Intel(R) Atom(TM) Processor Family?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x1C || \
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DisplayModel == 0x26 || \
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DisplayModel == 0x27 || \
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DisplayModel == 0x35 || \
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DisplayModel == 0x36 \
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) \
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)
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/**
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Shared. Model Specific Platform ID (R).
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@param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
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<b>Example usage</b>
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@code
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MSR_ATOM_PLATFORM_ID_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
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@endcode
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@note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
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**/
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#define MSR_ATOM_PLATFORM_ID 0x00000017
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/**
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MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:8;
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///
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/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
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///
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UINT32 MaximumQualifiedRatio:5;
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UINT32 Reserved2:19;
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UINT32 Reserved3:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_ATOM_PLATFORM_ID_REGISTER;
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/**
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Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
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processor features; (R) indicates current processor configuration.
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@param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
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<b>Example usage</b>
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@code
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MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
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AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
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@endcode
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@note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
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**/
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#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
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/**
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MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:1;
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///
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/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
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/// Always 0.
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///
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UINT32 DataErrorCheckingEnable:1;
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///
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/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
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/// Always 0.
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///
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UINT32 ResponseErrorCheckingEnable:1;
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///
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/// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
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///
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UINT32 AERR_DriveEnable:1;
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///
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/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
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/// Disabled Always 0.
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///
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UINT32 BERR_Enable:1;
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UINT32 Reserved2:1;
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UINT32 Reserved3:1;
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///
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/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
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///
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UINT32 BINIT_DriverEnable:1;
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UINT32 Reserved4:1;
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///
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/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 ExecuteBIST:1;
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///
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/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
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/// Always 0.
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///
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UINT32 AERR_ObservationEnabled:1;
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UINT32 Reserved5:1;
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///
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/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
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/// Always 0.
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///
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UINT32 BINIT_ObservationEnabled:1;
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UINT32 Reserved6:1;
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///
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/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
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///
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UINT32 ResetVector:1;
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UINT32 Reserved7:1;
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///
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/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
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///
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UINT32 APICClusterID:2;
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UINT32 Reserved8:2;
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///
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/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
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///
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UINT32 SymmetricArbitrationID:2;
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///
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/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
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///
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UINT32 IntegerBusFrequencyRatio:5;
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UINT32 Reserved9:5;
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UINT32 Reserved10:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_ATOM_EBL_CR_POWERON_REGISTER;
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/**
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Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
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record registers on the last branch record stack. The From_IP part of the
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stack contains pointers to the source instruction . See also: - Last Branch
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Record Stack TOS at 1C9H - Section 17.5.
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@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
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AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
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@endcode
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@note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
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MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
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@{
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**/
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#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
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#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
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#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
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#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
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#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
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#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
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#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
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#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
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/// @}
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/**
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Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
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record registers on the last branch record stack. The To_IP part of the
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stack contains pointers to the destination instruction.
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@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
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AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
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@endcode
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@note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
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MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
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@{
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**/
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#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
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#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
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#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
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#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
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#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
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#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
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#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
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#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
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/// @}
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/**
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Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
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bus clock speed for processors based on Intel Atom microarchitecture:.
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@param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
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<b>Example usage</b>
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@code
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MSR_ATOM_FSB_FREQ_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
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@endcode
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@note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
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**/
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#define MSR_ATOM_FSB_FREQ 0x000000CD
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/**
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MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 2:0] - Scalable Bus Speed
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///
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/// Atom Processor Family
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/// ---------------------
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/// 111B: 083 MHz (FSB 333)
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/// 101B: 100 MHz (FSB 400)
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/// 001B: 133 MHz (FSB 533)
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/// 011B: 167 MHz (FSB 667)
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///
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/// 133.33 MHz should be utilized if performing calculation with
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/// System Bus Speed when encoding is 001B.
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/// 166.67 MHz should be utilized if performing calculation with
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/// System Bus Speed when
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/// encoding is 011B.
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///
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UINT32 ScalableBusSpeed:3;
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UINT32 Reserved1:29;
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UINT32 Reserved2:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_ATOM_FSB_FREQ_REGISTER;
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/**
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Shared.
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@param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
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<b>Example usage</b>
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@code
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MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
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AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
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@endcode
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@note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
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**/
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#define MSR_ATOM_BBL_CR_CTL3 0x0000011E
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/**
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MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
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/// Indicates if the L2 is hardware-disabled.
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///
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UINT32 L2HardwareEnabled:1;
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UINT32 Reserved1:7;
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///
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/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
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/// Disabled (default) Until this bit is set the processor will not
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/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
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///
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UINT32 L2Enabled:1;
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UINT32 Reserved2:14;
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///
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/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
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///
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UINT32 L2NotPresent:1;
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UINT32 Reserved3:8;
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UINT32 Reserved4:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_ATOM_BBL_CR_CTL3_REGISTER;
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/**
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Shared.
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@param ECX MSR_ATOM_PERF_STATUS (0x00000198)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
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<b>Example usage</b>
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@code
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MSR_ATOM_PERF_STATUS_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
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AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
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@endcode
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@note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
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**/
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#define MSR_ATOM_PERF_STATUS 0x00000198
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/**
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MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 15:0] Current Performance State Value.
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///
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UINT32 CurrentPerformanceStateValue:16;
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UINT32 Reserved1:16;
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UINT32 Reserved2:8;
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///
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/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
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/// configured for the processor.
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///
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UINT32 MaximumBusRatio:5;
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UINT32 Reserved3:19;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_ATOM_PERF_STATUS_REGISTER;
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/**
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Shared.
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@param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
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<b>Example usage</b>
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@code
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MSR_ATOM_THERM2_CTL_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
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AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
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@endcode
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@note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
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**/
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#define MSR_ATOM_THERM2_CTL 0x0000019D
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/**
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MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:16;
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///
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/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
|
|
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
|
|
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
|
|
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
|
|
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
|
|
///
|
|
UINT32 TM_SELECT:1;
|
|
UINT32 Reserved2:15;
|
|
UINT32 Reserved3:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_ATOM_THERM2_CTL_REGISTER;
|
|
|
|
|
|
/**
|
|
Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
|
|
functions to be enabled and disabled.
|
|
|
|
@param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
|
|
AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
|
|
**/
|
|
#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
///
|
|
/// [Bit 0] Fast-Strings Enable See Table 35-2.
|
|
///
|
|
UINT32 FastStrings:1;
|
|
UINT32 Reserved1:2;
|
|
///
|
|
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
|
|
/// Table 35-2. Default value is 0.
|
|
///
|
|
UINT32 AutomaticThermalControlCircuit:1;
|
|
UINT32 Reserved2:3;
|
|
///
|
|
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
|
|
///
|
|
UINT32 PerformanceMonitoring:1;
|
|
UINT32 Reserved3:1;
|
|
UINT32 Reserved4:1;
|
|
///
|
|
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
|
|
/// the processor to indicate a pending break event within the processor 0
|
|
/// = Indicates compatible FERR# signaling behavior This bit must be set
|
|
/// to 1 to support XAPIC interrupt model usage.
|
|
///
|
|
UINT32 FERR:1;
|
|
///
|
|
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
|
|
///
|
|
UINT32 BTS:1;
|
|
///
|
|
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
|
|
/// Table 35-2.
|
|
///
|
|
UINT32 PEBS:1;
|
|
///
|
|
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
|
|
/// thermal sensor indicates that the die temperature is at the
|
|
/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
|
|
/// TM2 will reduce the bus to core ratio and voltage according to the
|
|
/// value last written to MSR_THERM2_CTL bits 15:0.
|
|
/// When this bit is clear (0, default), the processor does not change
|
|
/// the VID signals or the bus to core ratio when the processor enters a
|
|
/// thermally managed state. The BIOS must enable this feature if the
|
|
/// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
|
|
/// not set, this feature is not supported and BIOS must not alter the
|
|
/// contents of the TM2 bit location. The processor is operating out of
|
|
/// specification if both this bit and the TM1 bit are set to 0.
|
|
///
|
|
UINT32 TM2:1;
|
|
UINT32 Reserved5:2;
|
|
///
|
|
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
|
|
/// Table 35-2.
|
|
///
|
|
UINT32 EIST:1;
|
|
UINT32 Reserved6:1;
|
|
///
|
|
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
|
|
///
|
|
UINT32 MONITOR:1;
|
|
UINT32 Reserved7:1;
|
|
///
|
|
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
|
|
/// (R/WO) When set, this bit causes the following bits to become
|
|
/// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
|
|
/// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
|
|
/// be set before an Enhanced Intel SpeedStep Technology transition is
|
|
/// requested. This bit is cleared on reset.
|
|
///
|
|
UINT32 EISTLock:1;
|
|
UINT32 Reserved8:1;
|
|
///
|
|
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
|
|
///
|
|
UINT32 LimitCpuidMaxval:1;
|
|
///
|
|
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
|
|
///
|
|
UINT32 xTPR_Message_Disable:1;
|
|
UINT32 Reserved9:8;
|
|
UINT32 Reserved10:2;
|
|
///
|
|
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
|
|
///
|
|
UINT32 XD:1;
|
|
UINT32 Reserved11:29;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
|
|
|
|
|
|
/**
|
|
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
|
|
that points to the MSR containing the most recent branch record. See
|
|
MSR_LASTBRANCH_0_FROM_IP (at 40H).
|
|
|
|
@param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
|
|
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
|
|
@endcode
|
|
@note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
|
|
**/
|
|
#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
|
|
|
|
|
|
/**
|
|
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
|
|
last branch instruction that the processor executed prior to the last
|
|
exception that was generated or the last interrupt that was handled.
|
|
|
|
@param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
|
|
@endcode
|
|
@note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
|
|
**/
|
|
#define MSR_ATOM_LER_FROM_LIP 0x000001DD
|
|
|
|
|
|
/**
|
|
Unique. Last Exception Record To Linear IP (R) This area contains a pointer
|
|
to the target of the last branch instruction that the processor executed
|
|
prior to the last exception that was generated or the last interrupt that
|
|
was handled.
|
|
|
|
@param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
|
|
@endcode
|
|
@note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
|
|
**/
|
|
#define MSR_ATOM_LER_TO_LIP 0x000001DE
|
|
|
|
|
|
/**
|
|
Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
|
|
(PEBS).".
|
|
|
|
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
|
|
AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
|
|
**/
|
|
#define MSR_ATOM_PEBS_ENABLE 0x000003F1
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
///
|
|
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
|
|
///
|
|
UINT32 Enable:1;
|
|
UINT32 Reserved1:31;
|
|
UINT32 Reserved2:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_ATOM_PEBS_ENABLE_REGISTER;
|
|
|
|
|
|
/**
|
|
Package. Package C2 Residency Note: C-state values are processor specific
|
|
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
|
|
C-States. Package. Package C2 Residency Counter. (R/O) Time that this
|
|
package is in processor-specific C2 states since last reset. Counts at 1 Mhz
|
|
frequency.
|
|
|
|
@param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
|
|
|
|
|
|
/**
|
|
Package. Package C4 Residency Note: C-state values are processor specific
|
|
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
|
|
C-States. Package. Package C4 Residency Counter. (R/O) Time that this
|
|
package is in processor-specific C4 states since last reset. Counts at 1 Mhz
|
|
frequency.
|
|
|
|
@param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
|
|
|
|
|
|
/**
|
|
Package. Package C6 Residency Note: C-state values are processor specific
|
|
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
|
|
C-States. Package. Package C6 Residency Counter. (R/O) Time that this
|
|
package is in processor-specific C6 states since last reset. Counts at 1 Mhz
|
|
frequency.
|
|
|
|
@param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
|
|
|
|
#endif
|