307 lines
8.8 KiB
C
307 lines
8.8 KiB
C
/** @file
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MSR Definitions for Intel processors based on the Broadwell microarchitecture.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.
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**/
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#ifndef __BROADWELL_MSR_H__
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#define __BROADWELL_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Intel processors based on the Broadwell microarchitecture?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x3D || \
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DisplayModel == 0x47 || \
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DisplayModel == 0x4F || \
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DisplayModel == 0x56 \
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) \
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)
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/**
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Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
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Facilities.".
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@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
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<b>Example usage</b>
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@code
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MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
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AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
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@endcode
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@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
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**/
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#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E
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/**
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MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] Ovf_PMC0.
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///
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UINT32 Ovf_PMC0:1;
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///
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/// [Bit 1] Ovf_PMC1.
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///
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UINT32 Ovf_PMC1:1;
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///
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/// [Bit 2] Ovf_PMC2.
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///
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UINT32 Ovf_PMC2:1;
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///
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/// [Bit 3] Ovf_PMC3.
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///
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UINT32 Ovf_PMC3:1;
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UINT32 Reserved1:28;
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///
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/// [Bit 32] Ovf_FixedCtr0.
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///
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UINT32 Ovf_FixedCtr0:1;
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///
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/// [Bit 33] Ovf_FixedCtr1.
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///
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UINT32 Ovf_FixedCtr1:1;
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///
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/// [Bit 34] Ovf_FixedCtr2.
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///
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UINT32 Ovf_FixedCtr2:1;
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UINT32 Reserved2:20;
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///
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/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
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/// Addresses (ToPA).".
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///
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UINT32 Trace_ToPA_PMI:1;
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UINT32 Reserved3:5;
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///
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/// [Bit 61] Ovf_Uncore.
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///
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UINT32 Ovf_Uncore:1;
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///
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/// [Bit 62] Ovf_BufDSSAVE.
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///
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UINT32 OvfBuf:1;
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///
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/// [Bit 63] CondChgd.
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///
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UINT32 CondChgd:1;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
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/**
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Core. C-State Configuration Control (R/W) Note: C-state values are processor
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specific C-state code names, unrelated to MWAIT extension C-state parameters
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or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
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@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
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<b>Example usage</b>
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@code
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MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
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AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
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@endcode
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@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
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**/
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#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
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/**
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MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
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/// processor-specific C-state code name (consuming the least power) for
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/// the package. The default is set as factory-configured package C-state
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/// limit. The following C-state code name encodings are supported: 0000b:
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/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
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/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
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///
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UINT32 Limit:4;
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UINT32 Reserved1:6;
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///
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/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
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///
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UINT32 IO_MWAIT:1;
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UINT32 Reserved2:4;
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///
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/// [Bit 15] CFG Lock (R/WO).
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///
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UINT32 CFGLock:1;
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UINT32 Reserved3:9;
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///
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/// [Bit 25] C3 State Auto Demotion Enable (R/W).
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///
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UINT32 C3AutoDemotion:1;
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///
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/// [Bit 26] C1 State Auto Demotion Enable (R/W).
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///
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UINT32 C1AutoDemotion:1;
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///
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/// [Bit 27] Enable C3 Undemotion (R/W).
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///
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UINT32 C3Undemotion:1;
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///
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/// [Bit 28] Enable C1 Undemotion (R/W).
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///
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UINT32 C1Undemotion:1;
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///
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/// [Bit 29] Enable Package C-State Auto-demotion (R/W).
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///
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UINT32 CStateAutoDemotion:1;
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///
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/// [Bit 30] Enable Package C-State Undemotion (R/W).
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///
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UINT32 CStateUndemotion:1;
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UINT32 Reserved4:1;
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UINT32 Reserved5:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
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/**
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Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
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RW if MSR_PLATFORM_INFO.[28] = 1.
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@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
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<b>Example usage</b>
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@code
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MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
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@endcode
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@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
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**/
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#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD
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/**
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MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
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/// limit of 1 core active.
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///
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UINT32 Maximum1C:8;
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///
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/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
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/// limit of 2 core active.
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///
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UINT32 Maximum2C:8;
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///
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/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
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/// limit of 3 core active.
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///
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UINT32 Maximum3C:8;
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///
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/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
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/// limit of 4 core active.
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///
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UINT32 Maximum4C:8;
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///
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/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
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/// limit of 5core active.
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///
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UINT32 Maximum5C:8;
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///
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/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
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/// limit of 6core active.
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///
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UINT32 Maximum6C:8;
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UINT32 Reserved:16;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
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/**
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Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
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Domains.".
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@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
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@endcode
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@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
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**/
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#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639
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#endif
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