1111 lines
32 KiB
C
1111 lines
32 KiB
C
/** @file
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MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.
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**/
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#ifndef __CORE_MSR_H__
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#define __CORE_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Intel Core Solo and Intel Core Duo Processors?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x0E \
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) \
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)
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/**
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Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
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@param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
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AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
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@endcode
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@note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
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**/
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#define MSR_CORE_P5_MC_ADDR 0x00000000
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/**
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Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
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@param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
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AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
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@endcode
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@note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
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**/
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#define MSR_CORE_P5_MC_TYPE 0x00000001
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/**
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Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
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processor features; (R) indicates current processor configuration.
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@param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
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<b>Example usage</b>
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@code
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MSR_CORE_EBL_CR_POWERON_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
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AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
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@endcode
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@note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
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**/
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#define MSR_CORE_EBL_CR_POWERON 0x0000002A
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/**
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MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:1;
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///
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/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
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/// Note: Not all processor implements R/W.
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///
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UINT32 DataErrorCheckingEnable:1;
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///
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/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
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/// Note: Not all processor implements R/W.
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///
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UINT32 ResponseErrorCheckingEnable:1;
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///
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/// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
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/// all processor implements R/W.
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///
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UINT32 MCERR_DriveEnable:1;
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///
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/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
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/// Not all processor implements R/W.
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///
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UINT32 AddressParityEnable:1;
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UINT32 Reserved2:2;
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///
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/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
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/// all processor implements R/W.
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///
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UINT32 BINIT_DriverEnable:1;
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///
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/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 OutputTriStateEnable:1;
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///
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/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 ExecuteBIST:1;
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///
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/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 MCERR_ObservationEnabled:1;
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UINT32 Reserved3:1;
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///
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/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 BINIT_ObservationEnabled:1;
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UINT32 Reserved4:1;
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///
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/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
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///
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UINT32 ResetVector:1;
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UINT32 Reserved5:1;
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///
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/// [Bits 17:16] APIC Cluster ID (R/O).
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///
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UINT32 APICClusterID:2;
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///
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/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
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///
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UINT32 SystemBusFrequency:1;
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UINT32 Reserved6:1;
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///
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/// [Bits 21:20] Symmetric Arbitration ID (R/O).
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///
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UINT32 SymmetricArbitrationID:2;
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///
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/// [Bits 26:22] Clock Frequency Ratio (R/O).
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///
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UINT32 ClockFrequencyRatio:5;
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UINT32 Reserved7:5;
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UINT32 Reserved8:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_CORE_EBL_CR_POWERON_REGISTER;
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/**
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Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
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the last branch record stack: bits 31-0 hold the 'from' address and bits
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63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
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1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording
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(Pentium M Processors).".
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@param ECX MSR_CORE_LASTBRANCH_n
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
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AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
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@endcode
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@note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
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MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
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MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
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MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
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MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
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MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
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MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
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MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
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@{
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**/
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#define MSR_CORE_LASTBRANCH_0 0x00000040
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#define MSR_CORE_LASTBRANCH_1 0x00000041
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#define MSR_CORE_LASTBRANCH_2 0x00000042
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#define MSR_CORE_LASTBRANCH_3 0x00000043
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#define MSR_CORE_LASTBRANCH_4 0x00000044
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#define MSR_CORE_LASTBRANCH_5 0x00000045
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#define MSR_CORE_LASTBRANCH_6 0x00000046
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#define MSR_CORE_LASTBRANCH_7 0x00000047
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/// @}
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/**
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Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
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clock speed:.
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@param ECX MSR_CORE_FSB_FREQ (0x000000CD)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_CORE_FSB_FREQ_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_CORE_FSB_FREQ_REGISTER.
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<b>Example usage</b>
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@code
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MSR_CORE_FSB_FREQ_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
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@endcode
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@note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
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**/
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#define MSR_CORE_FSB_FREQ 0x000000CD
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/**
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MSR information returned for MSR index #MSR_CORE_FSB_FREQ
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 2:0] - Scalable Bus Speed
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/// 101B: 100 MHz (FSB 400)
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/// 001B: 133 MHz (FSB 533)
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/// 011B: 167 MHz (FSB 667)
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///
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/// 133.33 MHz should be utilized if performing calculation with System Bus
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/// Speed when encoding is 101B. 166.67 MHz should be utilized if
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/// performing calculation with System Bus Speed when encoding is 001B.
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///
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UINT32 ScalableBusSpeed:3;
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UINT32 Reserved1:29;
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UINT32 Reserved2:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_CORE_FSB_FREQ_REGISTER;
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/**
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Shared.
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@param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
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<b>Example usage</b>
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@code
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MSR_CORE_BBL_CR_CTL3_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
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AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
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@endcode
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@note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
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**/
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#define MSR_CORE_BBL_CR_CTL3 0x0000011E
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/**
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MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
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/// Indicates if the L2 is hardware-disabled.
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///
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UINT32 L2HardwareEnabled:1;
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UINT32 Reserved1:7;
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///
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/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
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/// Disabled (default) Until this bit is set the processor will not
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/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
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///
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UINT32 L2Enabled:1;
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UINT32 Reserved2:14;
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///
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/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
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///
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UINT32 L2NotPresent:1;
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UINT32 Reserved3:8;
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UINT32 Reserved4:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_CORE_BBL_CR_CTL3_REGISTER;
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/**
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Unique.
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@param ECX MSR_CORE_THERM2_CTL (0x0000019D)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_CORE_THERM2_CTL_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_CORE_THERM2_CTL_REGISTER.
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<b>Example usage</b>
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@code
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MSR_CORE_THERM2_CTL_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
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AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
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@endcode
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@note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
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**/
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#define MSR_CORE_THERM2_CTL 0x0000019D
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/**
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MSR information returned for MSR index #MSR_CORE_THERM2_CTL
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:16;
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///
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/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
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/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
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/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
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/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
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/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
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///
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UINT32 TM_SELECT:1;
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UINT32 Reserved2:15;
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UINT32 Reserved3:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_CORE_THERM2_CTL_REGISTER;
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/**
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Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
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functions to be enabled and disabled.
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@param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
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<b>Example usage</b>
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@code
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MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
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AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
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@endcode
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@note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
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**/
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#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
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/**
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MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:3;
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///
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/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
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/// Table 35-2.
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///
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UINT32 AutomaticThermalControlCircuit:1;
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UINT32 Reserved2:3;
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///
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/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
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///
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UINT32 PerformanceMonitoring:1;
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UINT32 Reserved3:2;
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///
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/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
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/// the processor to indicate a pending break event within the processor 0
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/// = Indicates compatible FERR# signaling behavior This bit must be set
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/// to 1 to support XAPIC interrupt model usage.
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///
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UINT32 FERR:1;
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///
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/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
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///
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UINT32 BTS:1;
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UINT32 Reserved4:1;
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///
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/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
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/// thermal sensor indicates that the die temperature is at the
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/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
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/// TM2 will reduce the bus to core ratio and voltage according to the
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/// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
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/// (0, default), the processor does not change the VID signals or the bus
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/// to core ratio when the processor enters a thermal managed state. If
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/// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
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/// with EAX = 1, then this feature is not supported and BIOS must not
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/// alter the contents of this bit location. The processor is operating
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/// out of spec if both this bit and the TM1 bit are set to disabled
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/// states.
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///
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UINT32 TM2:1;
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UINT32 Reserved5:2;
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///
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/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
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/// Enhanced Intel SpeedStep Technology enabled.
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///
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UINT32 EIST:1;
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UINT32 Reserved6:1;
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///
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/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
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///
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UINT32 MONITOR:1;
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UINT32 Reserved7:1;
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UINT32 Reserved8:2;
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///
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/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
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/// bit may cause behavior in software that depends on the availability of
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/// CPUID leaves greater than 2.
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///
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UINT32 LimitCpuidMaxval:1;
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UINT32 Reserved9:9;
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UINT32 Reserved10:2;
|
|
///
|
|
/// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.
|
|
///
|
|
UINT32 XD:1;
|
|
UINT32 Reserved11:29;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_CORE_IA32_MISC_ENABLE_REGISTER;
|
|
|
|
|
|
/**
|
|
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
|
|
that points to the MSR containing the most recent branch record. See
|
|
MSR_LASTBRANCH_0_FROM_IP (at 40H).
|
|
|
|
@param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
|
|
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
|
|
@endcode
|
|
@note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
|
|
**/
|
|
#define MSR_CORE_LASTBRANCH_TOS 0x000001C9
|
|
|
|
|
|
/**
|
|
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
|
|
last branch instruction that the processor executed prior to the last
|
|
exception that was generated or the last interrupt that was handled.
|
|
|
|
@param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
|
|
@endcode
|
|
@note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
|
|
**/
|
|
#define MSR_CORE_LER_FROM_LIP 0x000001DD
|
|
|
|
|
|
/**
|
|
Unique. Last Exception Record To Linear IP (R) This area contains a pointer
|
|
to the target of the last branch instruction that the processor executed
|
|
prior to the last exception that was generated or the last interrupt that
|
|
was handled.
|
|
|
|
@param ECX MSR_CORE_LER_TO_LIP (0x000001DE)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
|
|
@endcode
|
|
@note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
|
|
**/
|
|
#define MSR_CORE_LER_TO_LIP 0x000001DE
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
|
|
AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
|
|
**/
|
|
#define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
UINT32 Reserved1:2;
|
|
///
|
|
/// [Bit 2] Fast Strings Enable bit. (Default, enabled).
|
|
///
|
|
UINT32 FastStrings:1;
|
|
UINT32 Reserved2:29;
|
|
UINT32 Reserved3:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRPHYSBASEn
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
|
|
@{
|
|
**/
|
|
#define MSR_CORE_MTRRPHYSBASE0 0x00000200
|
|
#define MSR_CORE_MTRRPHYSBASE1 0x00000202
|
|
#define MSR_CORE_MTRRPHYSBASE2 0x00000204
|
|
#define MSR_CORE_MTRRPHYSBASE3 0x00000206
|
|
#define MSR_CORE_MTRRPHYSBASE4 0x00000208
|
|
#define MSR_CORE_MTRRPHYSBASE5 0x0000020A
|
|
#define MSR_CORE_MTRRPHYSMASK6 0x0000020D
|
|
#define MSR_CORE_MTRRPHYSMASK7 0x0000020F
|
|
/// @}
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
|
|
MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
|
|
MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
|
|
@{
|
|
**/
|
|
#define MSR_CORE_MTRRPHYSMASK0 0x00000201
|
|
#define MSR_CORE_MTRRPHYSMASK1 0x00000203
|
|
#define MSR_CORE_MTRRPHYSMASK2 0x00000205
|
|
#define MSR_CORE_MTRRPHYSMASK3 0x00000207
|
|
#define MSR_CORE_MTRRPHYSMASK4 0x00000209
|
|
#define MSR_CORE_MTRRPHYSMASK5 0x0000020B
|
|
#define MSR_CORE_MTRRPHYSBASE6 0x0000020C
|
|
#define MSR_CORE_MTRRPHYSBASE7 0x0000020E
|
|
/// @}
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX64K_00000 0x00000250
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX16K_80000 0x00000258
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX16K_A0000 0x00000259
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_C0000 0x00000268
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_C8000 0x00000269
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
|
|
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
|
|
**/
|
|
#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
|
|
|
|
|
|
/**
|
|
Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
|
|
|
|
@param ECX MSR_CORE_MC4_CTL (0x0000040C)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
|
|
AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
|
|
**/
|
|
#define MSR_CORE_MC4_CTL 0x0000040C
|
|
|
|
|
|
/**
|
|
Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
|
|
|
|
@param ECX MSR_CORE_MC4_STATUS (0x0000040D)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
|
|
AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
|
|
**/
|
|
#define MSR_CORE_MC4_STATUS 0x0000040D
|
|
|
|
|
|
/**
|
|
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
|
|
register is either not implemented or contains no address if the ADDRV flag
|
|
in the MSR_MC4_STATUS register is clear. When not implemented in the
|
|
processor, all reads and writes to this MSR will cause a general-protection
|
|
exception.
|
|
|
|
@param ECX MSR_CORE_MC4_ADDR (0x0000040E)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
|
|
AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
|
|
**/
|
|
#define MSR_CORE_MC4_ADDR 0x0000040E
|
|
|
|
|
|
/**
|
|
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
|
|
register is either not implemented or contains no address if the ADDRV flag
|
|
in the MSR_MC3_STATUS register is clear. When not implemented in the
|
|
processor, all reads and writes to this MSR will cause a general-protection
|
|
exception.
|
|
|
|
@param ECX MSR_CORE_MC3_ADDR (0x00000412)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
|
|
|
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<b>Example usage</b>
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|
@code
|
|
UINT64 Msr;
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|
|
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Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
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AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
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@endcode
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@note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
|
|
**/
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#define MSR_CORE_MC3_ADDR 0x00000412
|
|
|
|
|
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/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MC3_MISC (0x00000413)
|
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@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
|
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AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
|
|
**/
|
|
#define MSR_CORE_MC3_MISC 0x00000413
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MC5_CTL (0x00000414)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
|
|
AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
|
|
**/
|
|
#define MSR_CORE_MC5_CTL 0x00000414
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MC5_STATUS (0x00000415)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
|
|
AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
|
|
**/
|
|
#define MSR_CORE_MC5_STATUS 0x00000415
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MC5_ADDR (0x00000416)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
|
|
AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
|
|
**/
|
|
#define MSR_CORE_MC5_ADDR 0x00000416
|
|
|
|
|
|
/**
|
|
Unique.
|
|
|
|
@param ECX MSR_CORE_MC5_MISC (0x00000417)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
|
|
AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
|
|
@endcode
|
|
@note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
|
|
**/
|
|
#define MSR_CORE_MC5_MISC 0x00000417
|
|
|
|
|
|
/**
|
|
Unique. See Table 35-2.
|
|
|
|
@param ECX MSR_CORE_IA32_EFER (0xC0000080)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_CORE_IA32_EFER_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_CORE_IA32_EFER_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_CORE_IA32_EFER_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
|
|
AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
|
|
**/
|
|
#define MSR_CORE_IA32_EFER 0xC0000080
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_CORE_IA32_EFER
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
UINT32 Reserved1:11;
|
|
///
|
|
/// [Bit 11] Execute Disable Bit Enable.
|
|
///
|
|
UINT32 NXE:1;
|
|
UINT32 Reserved2:20;
|
|
UINT32 Reserved3:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_CORE_IA32_EFER_REGISTER;
|
|
|
|
#endif
|