685 lines
22 KiB
C
685 lines
22 KiB
C
/** @file
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MSR Definitions for Pentium M Processors.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.
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**/
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#ifndef __PENTIUM_M_MSR_H__
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#define __PENTIUM_M_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Pentium M Processors?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x0D \
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) \
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)
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/**
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See Section 35.22, "MSRs in Pentium Processors.".
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@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
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AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
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@endcode
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@note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
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**/
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#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
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/**
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See Section 35.22, "MSRs in Pentium Processors.".
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@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
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AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
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@endcode
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@note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
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**/
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#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
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/**
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Processor Hard Power-On Configuration (R/W) Enables and disables processor
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features. (R) Indicates current processor configuration.
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@param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
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<b>Example usage</b>
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@code
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MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
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AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
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@endcode
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@note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
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**/
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#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
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/**
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MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:1;
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///
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/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
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/// Pentium M processor.
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///
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UINT32 DataErrorCheckingEnable:1;
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///
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/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
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/// the Pentium M processor.
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///
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UINT32 ResponseErrorCheckingEnable:1;
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///
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/// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
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/// M processor.
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///
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UINT32 MCERR_DriveEnable:1;
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///
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/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
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/// M processor.
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///
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UINT32 AddressParityEnable:1;
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UINT32 Reserved2:2;
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///
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/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
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/// the Pentium M processor.
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///
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UINT32 BINIT_DriverEnable:1;
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///
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/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 OutputTriStateEnable:1;
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///
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/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
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///
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UINT32 ExecuteBIST:1;
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///
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/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
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/// Always 0 on the Pentium M processor.
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///
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UINT32 MCERR_ObservationEnabled:1;
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UINT32 Reserved3:1;
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///
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/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
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/// Always 0 on the Pentium M processor.
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///
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UINT32 BINIT_ObservationEnabled:1;
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UINT32 Reserved4:1;
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///
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/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
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/// Always 0 on the Pentium M processor.
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///
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UINT32 ResetVector:1;
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UINT32 Reserved5:1;
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///
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/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
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/// processor.
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///
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UINT32 APICClusterID:2;
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///
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/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
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/// 0 on the Pentium M processor.
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///
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UINT32 SystemBusFrequency:1;
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UINT32 Reserved6:1;
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///
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/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
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/// M processor.
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///
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UINT32 SymmetricArbitrationID:2;
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///
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/// [Bits 26:22] Clock Frequency Ratio (R/O).
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///
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UINT32 ClockFrequencyRatio:5;
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UINT32 Reserved7:5;
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UINT32 Reserved8:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
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/**
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Last Branch Record n (R/W) One of 8 last branch record registers on the last
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branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
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the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
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17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
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Processors)".
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@param ECX MSR_PENTIUM_M_LASTBRANCH_n
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
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AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
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@endcode
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@note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
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MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
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@{
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**/
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#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
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#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
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#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
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#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
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#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
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#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
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#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
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#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
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/// @}
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/**
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Reserved.
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@param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
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AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
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@endcode
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@note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
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**/
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#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
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/**
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@param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
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<b>Example usage</b>
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@code
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MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
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AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
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@endcode
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@note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
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**/
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#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
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/**
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MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
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/// Indicates if the L2 is hardware-disabled.
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///
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UINT32 L2HardwareEnabled:1;
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UINT32 Reserved1:4;
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///
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/// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
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/// cache data bus. ECC is always generated on write cycles. 1. = Disabled
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/// (default) 2. = Enabled For the Pentium M processor, ECC checking on
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/// the cache data bus is always enabled.
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///
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UINT32 ECCCheckEnable:1;
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UINT32 Reserved2:2;
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///
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/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
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/// Disabled (default) Until this bit is set the processor will not
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/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
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///
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UINT32 L2Enabled:1;
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UINT32 Reserved3:14;
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///
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/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
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///
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UINT32 L2NotPresent:1;
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UINT32 Reserved4:8;
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UINT32 Reserved5:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
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/**
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@param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
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<b>Example usage</b>
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@code
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MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
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AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
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@endcode
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@note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
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**/
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#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
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/**
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MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:16;
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///
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/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
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/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
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/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
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/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
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/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
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///
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UINT32 TM_SELECT:1;
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UINT32 Reserved2:15;
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UINT32 Reserved3:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
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/**
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Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
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functions to be enabled and disabled.
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@param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
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<b>Example usage</b>
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@code
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MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
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AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
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@endcode
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@note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
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**/
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#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
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/**
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MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:3;
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///
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/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
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/// this bit enables the thermal control circuit (TCC) portion of the
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/// Intel Thermal Monitor feature. This allows processor clocks to be
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/// automatically modulated based on the processor's thermal sensor
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/// operation. 0 = Disabled (default). The automatic thermal control
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/// circuit enable bit determines if the thermal control circuit (TCC)
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/// will be activated when the processor's internal thermal sensor
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/// determines the processor is about to exceed its maximum operating
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/// temperature. When the TCC is activated and TM1 is enabled, the
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/// processors clocks will be forced to a 50% duty cycle. BIOS must enable
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/// this feature. The bit should not be confused with the on-demand
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/// thermal control circuit enable bit.
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///
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UINT32 AutomaticThermalControlCircuit:1;
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UINT32 Reserved2:3;
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///
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/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
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/// monitoring enabled 0 = Performance monitoring disabled.
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///
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UINT32 PerformanceMonitoring:1;
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UINT32 Reserved3:2;
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///
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/// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
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/// processor to indicate a pending break event within the processor 0 =
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/// Indicates compatible FERR# signaling behavior This bit must be set to
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/// 1 to support XAPIC interrupt model usage.
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/// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
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/// support branch trace storage (BTS) 0 = BTS is supported
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///
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UINT32 FERR:1;
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///
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/// [Bit 11] Branch Trace Storage Unavailable (RO)
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/// 1 = Processor doesn't support branch trace storage (BTS)
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/// 0 = BTS is supported
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///
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UINT32 BTS:1;
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///
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/// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
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/// Processor does not support processor event based sampling (PEBS); 0 =
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/// PEBS is supported. The Pentium M processor does not support PEBS.
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///
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UINT32 PEBS:1;
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UINT32 Reserved5:3;
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///
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/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
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/// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
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/// processor, this bit may be configured to be read-only.
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///
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UINT32 EIST:1;
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UINT32 Reserved6:6;
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///
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/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
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/// disabled. xTPR messages are optional messages that allow the processor
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/// to inform the chipset of its priority. The default is processor
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/// specific.
|
|
///
|
|
UINT32 xTPR_Message_Disable:1;
|
|
UINT32 Reserved7:8;
|
|
UINT32 Reserved8:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
|
|
|
|
|
|
/**
|
|
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
|
|
to the MSR containing the most recent branch record. See also: -
|
|
MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
|
|
and Exception Recording (Pentium M Processors)".
|
|
|
|
@param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
|
|
|
|
|
|
/**
|
|
Debug Control (R/W) Controls how several debug features are used. Bit
|
|
definitions are discussed in the referenced section. See Section 17.13,
|
|
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
|
|
|
|
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
|
|
|
|
|
|
/**
|
|
Last Exception Record To Linear IP (R) This area contains a pointer to the
|
|
target of the last branch instruction that the processor executed prior to
|
|
the last exception that was generated or the last interrupt that was
|
|
handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording
|
|
(Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception
|
|
MSRs.".
|
|
|
|
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
|
|
|
|
|
|
/**
|
|
Last Exception Record From Linear IP (R) Contains a pointer to the last
|
|
branch instruction that the processor executed prior to the last exception
|
|
that was generated or the last interrupt that was handled. See Section
|
|
17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
|
|
Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".
|
|
|
|
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
|
|
|
|
|
|
/**
|
|
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
|
|
|
|
@param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
|
|
|
|
|
|
/**
|
|
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
|
|
|
|
@param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
|
|
|
|
|
|
/**
|
|
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
|
|
either not implemented or contains no address if the ADDRV flag in the
|
|
MSR_MC4_STATUS register is clear. When not implemented in the processor, all
|
|
reads and writes to this MSR will cause a general-protection exception.
|
|
|
|
@param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
|
|
|
|
|
|
/**
|
|
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
|
|
|
|
@param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_MC3_CTL 0x00000410
|
|
|
|
|
|
/**
|
|
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
|
|
|
|
@param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
|
|
|
|
|
|
/**
|
|
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
|
|
either not implemented or contains no address if the ADDRV flag in the
|
|
MSR_MC3_STATUS register is clear. When not implemented in the processor, all
|
|
reads and writes to this MSR will cause a general-protection exception.
|
|
|
|
@param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
|
|
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
|
|
@endcode
|
|
@note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
|
|
**/
|
|
#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
|
|
|
|
#endif
|