374 lines
12 KiB
C
374 lines
12 KiB
C
/** @file
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MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
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**/
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#ifndef __XEON_E7_MSR_H__
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#define __XEON_E7_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Intel(R) Xeon(R) Processor E7 Family?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x2F \
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) \
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)
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/**
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Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
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handler to handle unsuccessful read of this MSR.
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@param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
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AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
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@endcode
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@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
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**/
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#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C
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/**
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MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
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/// MSR, the configuration of AES instruction set availability is as
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/// follows: 11b: AES instructions are not available until next RESET.
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/// otherwise, AES instructions are available. Note, AES instruction set
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/// is not available if read is unsuccessful. If the configuration is not
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/// 01b, AES instruction can be mis-configured if a privileged agent
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/// unintentionally writes 11b.
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///
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UINT32 AESConfiguration:2;
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UINT32 Reserved1:30;
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UINT32 Reserved2:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
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/**
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Thread. Offcore Response Event Select Register (R/W).
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@param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
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AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
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@endcode
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@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
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**/
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#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7
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/**
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Package. Reserved Attempt to read/write will cause #UD.
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@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
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AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
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@endcode
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@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
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**/
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#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
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/**
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Package. Uncore C-box 8 perfmon local box control MSR.
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@param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
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AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
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@endcode
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@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
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**/
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#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
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/**
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Package. Uncore C-box 8 perfmon local box status MSR.
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@param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
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AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
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@endcode
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@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
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**/
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#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
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/**
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Package. Uncore C-box 8 perfmon local box overflow control MSR.
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@param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
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AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
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@endcode
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@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
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**/
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#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
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/**
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Package. Uncore C-box 8 perfmon event select MSR.
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@param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
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AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
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@endcode
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@note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
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MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
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MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
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MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
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MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
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MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
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@{
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**/
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#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
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#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
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#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
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#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
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#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
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#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
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/// @}
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/**
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Package. Uncore C-box 8 perfmon counter MSR.
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@param ECX MSR_XEON_E7_C8_PMON_CTRn
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
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AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
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@endcode
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@note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
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MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
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MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
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MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
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MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
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MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
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@{
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**/
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#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
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#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
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#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
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#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
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#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
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#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
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/// @}
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/**
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Package. Uncore C-box 9 perfmon local box control MSR.
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@param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
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AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
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@endcode
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@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
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**/
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#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
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/**
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Package. Uncore C-box 9 perfmon local box status MSR.
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@param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
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AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
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@endcode
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@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
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**/
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#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
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/**
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Package. Uncore C-box 9 perfmon local box overflow control MSR.
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@param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
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AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
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@endcode
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@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
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**/
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#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
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/**
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Package. Uncore C-box 9 perfmon event select MSR.
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@param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
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AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
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@endcode
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@note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
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MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
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MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
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MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
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MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
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MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
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@{
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**/
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#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
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#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
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#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
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#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
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#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
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#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
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/// @}
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/**
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Package. Uncore C-box 9 perfmon counter MSR.
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@param ECX MSR_XEON_E7_C9_PMON_CTRn
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
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AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
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@endcode
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@note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
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MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
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MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
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MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
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MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
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MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
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@{
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**/
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#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
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#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
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#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
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#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
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#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
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#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB
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/// @}
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#endif
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