1406 lines
41 KiB
C
1406 lines
41 KiB
C
/** @file
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MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.
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**/
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#ifndef __XEON_PHI_MSR_H__
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#define __XEON_PHI_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Intel(R) Xeon(R) Phi(TM) processor Family?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x57 \
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) \
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)
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/**
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Thread. SMI Counter (R/O).
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@param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
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@endcode
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@note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
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**/
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#define MSR_XEON_PHI_SMI_COUNT 0x00000034
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 31:0] SMI Count (R/O).
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///
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UINT32 SMICount:32;
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UINT32 Reserved:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_SMI_COUNT_REGISTER;
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/**
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Package. See http://biosbits.org.
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@param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
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AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
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**/
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#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:8;
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///
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/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
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/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
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/// MHz.
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///
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UINT32 MaximumNonTurboRatio:8;
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UINT32 Reserved2:12;
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///
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/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
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/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
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/// enabled, and when set to 0, indicates Programmable Ratio Limits for
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/// Turbo mode is disabled.
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///
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UINT32 RatioLimit:1;
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///
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/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
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/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
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/// and when set to 0, indicates TDP Limit for Turbo mode is not
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/// programmable.
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///
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UINT32 TDPLimit:1;
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UINT32 Reserved3:2;
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UINT32 Reserved4:8;
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///
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/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
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/// minimum ratio (maximum efficiency) that the processor can operates, in
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/// units of 100MHz.
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///
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UINT32 MaximumEfficiencyRatio:8;
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UINT32 Reserved5:16;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
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/**
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Module. C-State Configuration Control (R/W).
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@param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
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AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
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**/
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#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
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/// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
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/// Retention 011b: C6 Retention 111b: No limit.
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///
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UINT32 Limit:3;
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UINT32 Reserved1:7;
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///
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/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
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///
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UINT32 IO_MWAIT:1;
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UINT32 Reserved2:4;
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///
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/// [Bit 15] CFG Lock (R/WO).
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///
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UINT32 CFGLock:1;
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UINT32 Reserved3:16;
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UINT32 Reserved4:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
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/**
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Module. Power Management IO Redirection in C-state (R/W).
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@param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
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AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
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**/
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#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 15:0] LVL_2 Base Address (R/W).
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///
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UINT32 Lvl2Base:16;
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///
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/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
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/// maximum C-State code name to be included when IO read to MWAIT
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/// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
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/// is the max C-State to include 110b - C6 is the max C-State to include.
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///
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UINT32 CStateRange:3;
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UINT32 Reserved1:13;
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UINT32 Reserved2:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
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/**
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Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
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handler to handle unsuccessful read of this MSR.
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@param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
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AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
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**/
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#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
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/// MSR, the configuration of AES instruction set availability is as
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/// follows: 11b: AES instructions are not available until next RESET.
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/// otherwise, AES instructions are available. Note, AES instruction set
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/// is not available if read is unsuccessful. If the configuration is not
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/// 01b, AES instruction can be mis-configured if a privileged agent
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/// unintentionally writes 11b.
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///
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UINT32 AESConfiguration:2;
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UINT32 Reserved1:30;
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UINT32 Reserved2:32;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
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/**
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THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
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Enhancement. Accessible only while in SMM.
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@param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
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AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
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**/
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#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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UINT32 Reserved1:32;
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UINT32 Reserved2:26;
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///
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/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
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/// SMM code access restriction is supported and a host-space interface
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/// available to SMM handler.
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///
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UINT32 SMM_Code_Access_Chk:1;
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///
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/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
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/// SMM long flow indicator is supported and a host-space interface
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/// available to SMM handler.
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///
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UINT32 Long_Flow_Indication:1;
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UINT32 Reserved3:4;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;
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/**
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Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
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functions to be enabled and disabled.
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@param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
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AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
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**/
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#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
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/**
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MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] Fast-Strings Enable.
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///
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UINT32 FastStrings:1;
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UINT32 Reserved1:2;
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///
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/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
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/// is 1.
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///
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UINT32 AutomaticThermalControlCircuit:1;
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UINT32 Reserved2:3;
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///
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/// [Bit 7] Performance Monitoring Available (R).
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///
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UINT32 PerformanceMonitoring:1;
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UINT32 Reserved3:3;
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///
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/// [Bit 11] Branch Trace Storage Unavailable (RO).
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///
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UINT32 BTS:1;
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///
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/// [Bit 12] Processor Event Based Sampling Unavailable (RO).
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///
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UINT32 PEBS:1;
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UINT32 Reserved4:3;
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///
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/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
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///
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UINT32 EIST:1;
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UINT32 Reserved5:1;
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///
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/// [Bit 18] ENABLE MONITOR FSM (R/W).
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///
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UINT32 MONITOR:1;
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UINT32 Reserved6:3;
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///
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/// [Bit 22] Limit CPUID Maxval (R/W).
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///
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UINT32 LimitCpuidMaxval:1;
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///
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/// [Bit 23] xTPR Message Disable (R/W).
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///
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UINT32 xTPR_Message_Disable:1;
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UINT32 Reserved7:8;
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UINT32 Reserved8:2;
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///
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/// [Bit 34] XD Bit Disable (R/W).
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///
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UINT32 XD:1;
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UINT32 Reserved9:3;
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///
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/// [Bit 38] Turbo Mode Disable (R/W).
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///
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UINT32 TurboModeDisable:1;
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UINT32 Reserved10:25;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
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/**
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Package.
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@param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
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<b>Example usage</b>
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@code
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MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
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AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
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@endcode
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@note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
UINT32 Reserved1:16;
|
|
///
|
|
/// [Bits 23:16] Temperature Target (R).
|
|
///
|
|
UINT32 TemperatureTarget:8;
|
|
///
|
|
/// [Bits 29:24] Target Offset (R/W).
|
|
///
|
|
UINT32 TargetOffset:6;
|
|
UINT32 Reserved2:2;
|
|
UINT32 Reserved3:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
|
|
|
|
|
|
/**
|
|
Miscellaneous Feature Control (R/W).
|
|
|
|
@param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
///
|
|
/// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
|
|
/// L1 data cache prefetcher.
|
|
///
|
|
UINT32 DCUHardwarePrefetcherDisable:1;
|
|
///
|
|
/// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
|
|
/// L2 hardware prefetcher.
|
|
///
|
|
UINT32 L2HardwarePrefetcherDisable:1;
|
|
UINT32 Reserved1:30;
|
|
UINT32 Reserved2:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;
|
|
|
|
|
|
/**
|
|
Shared. Offcore Response Event Select Register (R/W).
|
|
|
|
@param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
|
|
|
|
|
|
/**
|
|
Shared. Offcore Response Event Select Register (R/W).
|
|
|
|
@param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
|
|
|
|
|
|
/**
|
|
Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
|
|
|
|
@param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
UINT32 Reserved:1;
|
|
///
|
|
/// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
|
|
/// processor cores which operates under the maximum ratio limit for group
|
|
/// 0.
|
|
///
|
|
UINT32 MaxCoresGroup0:7;
|
|
///
|
|
/// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
|
|
/// ratio limit when the number of active cores are not more than the
|
|
/// group 0 maximum core count.
|
|
///
|
|
UINT32 MaxRatioLimitGroup0:8;
|
|
///
|
|
/// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
|
|
/// Group 1, which includes the specified number of additional cores plus
|
|
/// the cores in group 0, operates under the group 1 turbo max ratio limit
|
|
/// = "group 0 Max ratio limit" - "group ratio delta for group 1".
|
|
///
|
|
UINT32 MaxIncrementalCoresGroup1:5;
|
|
///
|
|
/// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
|
|
/// integer specifying the ratio decrement relative to the Max ratio limit
|
|
/// to Group 0.
|
|
///
|
|
UINT32 DeltaRatioGroup1:3;
|
|
///
|
|
/// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
|
|
/// Group 2, which includes the specified number of additional cores plus
|
|
/// all the cores in group 1, operates under the group 2 turbo max ratio
|
|
/// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
|
|
///
|
|
UINT32 MaxIncrementalCoresGroup2:5;
|
|
///
|
|
/// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
|
|
/// integer specifying the ratio decrement relative to the Max ratio limit
|
|
/// for Group 1.
|
|
///
|
|
UINT32 DeltaRatioGroup2:3;
|
|
///
|
|
/// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
|
|
/// Group 3, which includes the specified number of additional cores plus
|
|
/// all the cores in group 2, operates under the group 3 turbo max ratio
|
|
/// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
|
|
///
|
|
UINT32 MaxIncrementalCoresGroup3:5;
|
|
///
|
|
/// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
|
|
/// integer specifying the ratio decrement relative to the Max ratio limit
|
|
/// for Group 2.
|
|
///
|
|
UINT32 DeltaRatioGroup3:3;
|
|
///
|
|
/// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
|
|
/// Group 4, which includes the specified number of additional cores plus
|
|
/// all the cores in group 3, operates under the group 4 turbo max ratio
|
|
/// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
|
|
///
|
|
UINT32 MaxIncrementalCoresGroup4:5;
|
|
///
|
|
/// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
|
|
/// integer specifying the ratio decrement relative to the Max ratio limit
|
|
/// for Group 3.
|
|
///
|
|
UINT32 DeltaRatioGroup4:3;
|
|
///
|
|
/// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
|
|
/// Group 5, which includes the specified number of additional cores plus
|
|
/// all the cores in group 4, operates under the group 5 turbo max ratio
|
|
/// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
|
|
///
|
|
UINT32 MaxIncrementalCoresGroup5:5;
|
|
///
|
|
/// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
|
|
/// integer specifying the ratio decrement relative to the Max ratio limit
|
|
/// for Group 4.
|
|
///
|
|
UINT32 DeltaRatioGroup5:3;
|
|
///
|
|
/// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
|
|
/// Group 6, which includes the specified number of additional cores plus
|
|
/// all the cores in group 5, operates under the group 6 turbo max ratio
|
|
/// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
|
|
///
|
|
UINT32 MaxIncrementalCoresGroup6:5;
|
|
///
|
|
/// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
|
|
/// integer specifying the ratio decrement relative to the Max ratio limit
|
|
/// for Group 5.
|
|
///
|
|
UINT32 DeltaRatioGroup6:3;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
|
|
|
|
|
|
/**
|
|
Thread. Last Branch Record Filtering Select Register (R/W).
|
|
|
|
@param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
|
|
|
|
|
|
/**
|
|
Thread. Last Branch Record Stack TOS (R/W).
|
|
|
|
@param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
|
|
|
|
|
|
/**
|
|
Thread. Last Exception Record From Linear IP (R).
|
|
|
|
@param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
|
|
@endcode
|
|
@note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
|
|
|
|
|
|
/**
|
|
Thread. Last Exception Record To Linear IP (R).
|
|
|
|
@param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
|
|
@endcode
|
|
@note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
|
|
|
|
|
|
/**
|
|
Thread. See Table 35-2.
|
|
|
|
@param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
|
|
|
|
|
|
/**
|
|
Package. Note: C-state values are processor specific C-state code names,
|
|
unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
|
|
Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
|
|
|
|
|
|
/**
|
|
Package. Package C6 Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
|
|
|
|
|
|
/**
|
|
Package. Package C7 Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
|
|
|
|
|
|
/**
|
|
Module. Note: C-state values are processor specific C-state code names,
|
|
unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
|
|
Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
|
|
|
|
|
|
/**
|
|
Module. Module C6 Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
|
|
|
|
|
|
/**
|
|
Core. Note: C-state values are processor specific C-state code names,
|
|
unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
|
|
Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
|
|
|
|
|
|
/**
|
|
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
|
|
|
|
@param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
|
|
@endcode
|
|
@note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
|
|
|
|
|
|
/**
|
|
Core. Capability Reporting Register of VM-function Controls (R/O) See Table
|
|
35-2.
|
|
|
|
@param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
|
|
@endcode
|
|
@note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
|
|
|
|
|
|
/**
|
|
Package. Unit Multipliers used in RAPL Interfaces (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
|
|
@endcode
|
|
@note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
///
|
|
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
|
|
///
|
|
UINT32 PowerUnits:4;
|
|
UINT32 Reserved1:4;
|
|
///
|
|
/// [Bits 12:8] Package. Energy Status Units Energy related information
|
|
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
|
|
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
|
|
/// micro-joules).
|
|
///
|
|
UINT32 EnergyStatusUnits:5;
|
|
UINT32 Reserved2:3;
|
|
///
|
|
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
|
|
/// Interfaces.".
|
|
///
|
|
UINT32 TimeUnits:4;
|
|
UINT32 Reserved3:12;
|
|
UINT32 Reserved4:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
|
|
|
|
|
|
/**
|
|
Package. Note: C-state values are processor specific C-state code names,
|
|
unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
|
|
Residency Counter. (R/O).
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
|
|
|
|
|
|
/**
|
|
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
|
|
RAPL Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
|
|
|
|
|
|
/**
|
|
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
|
|
|
|
|
|
/**
|
|
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
|
|
|
|
|
|
/**
|
|
Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
|
|
Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
|
|
|
|
|
|
/**
|
|
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
|
|
Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
|
|
|
|
|
|
/**
|
|
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
|
|
@endcode
|
|
@note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
|
|
|
|
|
|
/**
|
|
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
|
|
RAPL Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
|
|
@endcode
|
|
@note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
|
|
|
|
|
|
/**
|
|
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
|
|
|
|
@param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
|
|
|
|
|
|
/**
|
|
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
|
|
RAPL Domains.".
|
|
|
|
@param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
|
|
|
|
|
|
/**
|
|
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
|
|
Domains.".
|
|
|
|
@param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
|
|
@endcode
|
|
@note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
|
|
|
|
|
|
/**
|
|
Package. Base TDP Ratio (R/O) See Table 35-23.
|
|
|
|
@param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
|
|
@endcode
|
|
@note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
|
|
|
|
|
|
/**
|
|
Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.
|
|
|
|
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
|
|
@endcode
|
|
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
|
|
|
|
|
|
/**
|
|
Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.
|
|
|
|
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
|
|
@endcode
|
|
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
|
|
|
|
|
|
/**
|
|
Package. ConfigTDP Control (R/W) See Table 35-23.
|
|
|
|
@param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
|
|
|
|
|
|
/**
|
|
Package. ConfigTDP Control (R/W) See Table 35-23.
|
|
|
|
@param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
UINT64 Msr;
|
|
|
|
Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
|
|
@endcode
|
|
@note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
|
|
|
|
|
|
/**
|
|
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
|
|
refers to processor core frequency).
|
|
|
|
@param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
|
|
@param EAX Lower 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
|
|
@param EDX Upper 32-bits of MSR value.
|
|
Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
|
|
|
|
<b>Example usage</b>
|
|
@code
|
|
MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
|
|
|
|
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
|
|
AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
|
|
@endcode
|
|
@note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
|
|
**/
|
|
#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
|
|
|
|
/**
|
|
MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
|
|
**/
|
|
typedef union {
|
|
///
|
|
/// Individual bit fields
|
|
///
|
|
struct {
|
|
///
|
|
/// [Bit 0] PROCHOT Status (R0).
|
|
///
|
|
UINT32 PROCHOT_Status:1;
|
|
///
|
|
/// [Bit 1] Thermal Status (R0).
|
|
///
|
|
UINT32 ThermalStatus:1;
|
|
UINT32 Reserved1:4;
|
|
///
|
|
/// [Bit 6] VR Therm Alert Status (R0).
|
|
///
|
|
UINT32 VRThermAlertStatus:1;
|
|
UINT32 Reserved2:1;
|
|
///
|
|
/// [Bit 8] Electrical Design Point Status (R0).
|
|
///
|
|
UINT32 ElectricalDesignPointStatus:1;
|
|
UINT32 Reserved3:23;
|
|
UINT32 Reserved4:32;
|
|
} Bits;
|
|
///
|
|
/// All bit fields as a 32-bit value
|
|
///
|
|
UINT32 Uint32;
|
|
///
|
|
/// All bit fields as a 64-bit value
|
|
///
|
|
UINT64 Uint64;
|
|
} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
|
|
|
|
#endif
|