mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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696 lines
26 KiB
C
696 lines
26 KiB
C
/** @file
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Support for the latest PCI standard.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIEXPRESS21_H_
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#define _PCIEXPRESS21_H_
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#include <IndustryStandard/Pci30.h>
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/**
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Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
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ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
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of Bus, Device, Function and Register are stripped prior to the generation of
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the address.
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@param Bus PCI Bus number. Range 0..255.
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@param Device PCI Device number. Range 0..31.
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@param Function PCI Function number. Range 0..7.
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@param Register PCI Register number. Range 0..4095.
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@return The encode ECAM address.
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**/
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#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
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(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
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#pragma pack(1)
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///
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/// PCI Express Capability Structure
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///
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typedef union {
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struct {
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UINT16 Version : 4;
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UINT16 DevicePortType : 4;
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UINT16 SlotImplemented : 1;
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UINT16 InterruptMessageNumber : 5;
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UINT16 Undefined : 1;
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UINT16 Reserved : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_CAPABILITY;
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#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
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#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
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#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
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#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
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#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
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#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
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#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
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#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
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#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
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typedef union {
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struct {
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UINT32 MaxPayloadSize : 3;
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UINT32 PhantomFunctions : 2;
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UINT32 ExtendedTagField : 1;
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UINT32 EndpointL0sAcceptableLatency : 3;
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UINT32 EndpointL1AcceptableLatency : 3;
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UINT32 Undefined : 3;
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UINT32 RoleBasedErrorReporting : 1;
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UINT32 Reserved : 2;
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UINT32 CapturedSlotPowerLimitValue : 8;
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UINT32 CapturedSlotPowerLimitScale : 2;
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UINT32 FunctionLevelReset : 1;
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UINT32 Reserved2 : 3;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_CAPABILITY;
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typedef union {
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struct {
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UINT16 CorrectableError : 1;
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UINT16 NonFatalError : 1;
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UINT16 FatalError : 1;
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UINT16 UnsupportedRequest : 1;
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UINT16 RelaxedOrdering : 1;
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UINT16 MaxPayloadSize : 3;
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UINT16 ExtendedTagField : 1;
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UINT16 PhantomFunctions : 1;
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UINT16 AuxPower : 1;
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UINT16 NoSnoop : 1;
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UINT16 MaxReadRequestSize : 3;
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UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_DEVICE_CONTROL;
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#define PCIE_MAX_PAYLOAD_SIZE_128B 0
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#define PCIE_MAX_PAYLOAD_SIZE_256B 1
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#define PCIE_MAX_PAYLOAD_SIZE_512B 2
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#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
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#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
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#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
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#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
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#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
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#define PCIE_MAX_READ_REQ_SIZE_128B 0
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#define PCIE_MAX_READ_REQ_SIZE_256B 1
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#define PCIE_MAX_READ_REQ_SIZE_512B 2
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#define PCIE_MAX_READ_REQ_SIZE_1024B 3
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#define PCIE_MAX_READ_REQ_SIZE_2048B 4
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#define PCIE_MAX_READ_REQ_SIZE_4096B 5
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#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
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#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
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typedef union {
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struct {
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UINT16 CorrectableError : 1;
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UINT16 NonFatalError : 1;
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UINT16 FatalError : 1;
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UINT16 UnsupportedRequest : 1;
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UINT16 AuxPower : 1;
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UINT16 TransactionsPending : 1;
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UINT16 Reserved : 10;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_DEVICE_STATUS;
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typedef union {
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struct {
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UINT32 MaxLinkSpeed : 4;
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UINT32 MaxLinkWidth : 6;
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UINT32 Aspm : 2;
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UINT32 L0sExitLatency : 3;
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UINT32 L1ExitLatency : 3;
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UINT32 ClockPowerManagement : 1;
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UINT32 SurpriseDownError : 1;
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UINT32 DataLinkLayerLinkActive : 1;
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UINT32 LinkBandwidthNotification : 1;
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UINT32 AspmOptionalityCompliance : 1;
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UINT32 Reserved : 1;
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UINT32 PortNumber : 8;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_LINK_CAPABILITY;
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#define PCIE_LINK_ASPM_L0S BIT0
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#define PCIE_LINK_ASPM_L1 BIT1
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typedef union {
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struct {
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UINT16 AspmControl : 2;
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UINT16 Reserved : 1;
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UINT16 ReadCompletionBoundary : 1;
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UINT16 LinkDisable : 1;
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UINT16 RetrainLink : 1;
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UINT16 CommonClockConfiguration : 1;
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UINT16 ExtendedSynch : 1;
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UINT16 ClockPowerManagement : 1;
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UINT16 HardwareAutonomousWidthDisable : 1;
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UINT16 LinkBandwidthManagementInterrupt : 1;
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UINT16 LinkAutonomousBandwidthInterrupt : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_CONTROL;
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typedef union {
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struct {
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UINT16 CurrentLinkSpeed : 4;
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UINT16 NegotiatedLinkWidth : 6;
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UINT16 Undefined : 1;
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UINT16 LinkTraining : 1;
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UINT16 SlotClockConfiguration : 1;
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UINT16 DataLinkLayerLinkActive : 1;
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UINT16 LinkBandwidthManagement : 1;
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UINT16 LinkAutonomousBandwidth : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_STATUS;
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typedef union {
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struct {
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UINT32 AttentionButton : 1;
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UINT32 PowerController : 1;
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UINT32 MrlSensor : 1;
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UINT32 AttentionIndicator : 1;
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UINT32 PowerIndicator : 1;
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UINT32 HotPlugSurprise : 1;
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UINT32 HotPlugCapable : 1;
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UINT32 SlotPowerLimitValue : 8;
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UINT32 SlotPowerLimitScale : 2;
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UINT32 ElectromechanicalInterlock : 1;
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UINT32 NoCommandCompleted : 1;
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UINT32 PhysicalSlotNumber : 13;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_SLOT_CAPABILITY;
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typedef union {
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struct {
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UINT16 AttentionButtonPressed : 1;
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UINT16 PowerFaultDetected : 1;
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UINT16 MrlSensorChanged : 1;
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UINT16 PresenceDetectChanged : 1;
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UINT16 CommandCompletedInterrupt : 1;
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UINT16 HotPlugInterrupt : 1;
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UINT16 AttentionIndicator : 2;
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UINT16 PowerIndicator : 2;
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UINT16 PowerController : 1;
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UINT16 ElectromechanicalInterlock : 1;
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UINT16 DataLinkLayerStateChanged : 1;
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UINT16 Reserved : 3;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_SLOT_CONTROL;
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typedef union {
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struct {
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UINT16 AttentionButtonPressed : 1;
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UINT16 PowerFaultDetected : 1;
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UINT16 MrlSensorChanged : 1;
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UINT16 PresenceDetectChanged : 1;
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UINT16 CommandCompleted : 1;
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UINT16 MrlSensor : 1;
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UINT16 PresenceDetect : 1;
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UINT16 ElectromechanicalInterlock : 1;
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UINT16 DataLinkLayerStateChanged : 1;
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UINT16 Reserved : 7;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_SLOT_STATUS;
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typedef union {
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struct {
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UINT16 SystemErrorOnCorrectableError : 1;
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UINT16 SystemErrorOnNonFatalError : 1;
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UINT16 SystemErrorOnFatalError : 1;
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UINT16 PmeInterrupt : 1;
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UINT16 CrsSoftwareVisibility : 1;
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UINT16 Reserved : 11;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_ROOT_CONTROL;
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typedef union {
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struct {
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UINT16 CrsSoftwareVisibility : 1;
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UINT16 Reserved : 15;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_ROOT_CAPABILITY;
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typedef union {
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struct {
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UINT32 PmeRequesterId : 16;
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UINT32 PmeStatus : 1;
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UINT32 PmePending : 1;
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UINT32 Reserved : 14;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_ROOT_STATUS;
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typedef union {
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struct {
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UINT32 CompletionTimeoutRanges : 4;
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UINT32 CompletionTimeoutDisable : 1;
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UINT32 AriForwarding : 1;
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UINT32 AtomicOpRouting : 1;
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UINT32 AtomicOp32Completer : 1;
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UINT32 AtomicOp64Completer : 1;
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UINT32 Cas128Completer : 1;
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UINT32 NoRoEnabledPrPrPassing : 1;
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UINT32 LtrMechanism : 1;
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UINT32 TphCompleter : 2;
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UINT32 LnSystemCLS : 2;
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UINT32 TenBitTagCompleterSupported : 1;
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UINT32 TenBitTagRequesterSupported : 1;
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UINT32 Obff : 2;
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UINT32 ExtendedFmtField : 1;
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UINT32 EndEndTlpPrefix : 1;
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UINT32 MaxEndEndTlpPrefixes : 2;
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UINT32 EmergencyPowerReductionSupported : 2;
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UINT32 EmergencyPowerReductionInitializationRequired : 1;
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UINT32 Reserved3 : 4;
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UINT32 FrsSupported : 1;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_CAPABILITY2;
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#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
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#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
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#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
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#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
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#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
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#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
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#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
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#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
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#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
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#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
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typedef union {
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struct {
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UINT16 CompletionTimeoutValue : 4;
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UINT16 CompletionTimeoutDisable : 1;
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UINT16 AriForwarding : 1;
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UINT16 AtomicOpRequester : 1;
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UINT16 AtomicOpEgressBlocking : 1;
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UINT16 IdoRequest : 1;
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UINT16 IdoCompletion : 1;
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UINT16 LtrMechanism : 2;
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UINT16 EmergencyPowerReductionRequest : 1;
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UINT16 TenBitTagRequesterEnable : 1;
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UINT16 Obff : 2;
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UINT16 EndEndTlpPrefixBlocking : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_DEVICE_CONTROL2;
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#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
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#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
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#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
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#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
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#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
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#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
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#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
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#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
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#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
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#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
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#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
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#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
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#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
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typedef union {
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struct {
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UINT32 Reserved : 1;
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UINT32 LinkSpeedsVector : 7;
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UINT32 Crosslink : 1;
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UINT32 Reserved2 : 23;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_LINK_CAPABILITY2;
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typedef union {
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struct {
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UINT16 TargetLinkSpeed : 4;
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UINT16 EnterCompliance : 1;
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UINT16 HardwareAutonomousSpeedDisable : 1;
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UINT16 SelectableDeemphasis : 1;
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UINT16 TransmitMargin : 3;
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UINT16 EnterModifiedCompliance : 1;
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UINT16 ComplianceSos : 1;
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UINT16 CompliancePresetDeemphasis : 4;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_CONTROL2;
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typedef union {
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struct {
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UINT16 CurrentDeemphasisLevel : 1;
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UINT16 EqualizationComplete : 1;
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UINT16 EqualizationPhase1Successful : 1;
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UINT16 EqualizationPhase2Successful : 1;
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UINT16 EqualizationPhase3Successful : 1;
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UINT16 LinkEqualizationRequest : 1;
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UINT16 Reserved : 10;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_STATUS2;
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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PCI_REG_PCIE_CAPABILITY Capability;
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PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
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PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
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PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
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PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
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PCI_REG_PCIE_LINK_CONTROL LinkControl;
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PCI_REG_PCIE_LINK_STATUS LinkStatus;
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PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
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PCI_REG_PCIE_SLOT_CONTROL SlotControl;
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PCI_REG_PCIE_SLOT_STATUS SlotStatus;
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PCI_REG_PCIE_ROOT_CONTROL RootControl;
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PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
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PCI_REG_PCIE_ROOT_STATUS RootStatus;
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PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
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PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
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UINT16 DeviceStatus2;
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PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
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PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
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PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
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UINT32 SlotCapability2;
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UINT16 SlotControl2;
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UINT16 SlotStatus2;
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} PCI_CAPABILITY_PCIEXP;
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#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
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#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
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#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
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#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
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#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
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//
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// for SR-IOV
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//
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#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
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#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
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#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
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#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
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typedef struct {
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UINT32 CapabilityHeader;
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UINT32 Capability;
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UINT16 Control;
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UINT16 Status;
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UINT16 InitialVFs;
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UINT16 TotalVFs;
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UINT16 NumVFs;
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UINT8 FunctionDependencyLink;
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UINT8 Reserved0;
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UINT16 FirstVFOffset;
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UINT16 VFStride;
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UINT16 Reserved1;
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UINT16 VFDeviceID;
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UINT32 SupportedPageSize;
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UINT32 SystemPageSize;
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UINT32 VFBar[6];
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UINT32 VFMigrationStateArrayOffset;
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} SR_IOV_CAPABILITY_REGISTER;
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
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typedef struct {
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UINT32 CapabilityId:16;
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UINT32 CapabilityVersion:4;
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UINT32 NextCapabilityOffset:12;
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} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
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#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
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typedef union {
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struct {
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UINT32 Undefined : 1;
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UINT32 Reserved : 3;
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UINT32 DataLinkProtocolError : 1;
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UINT32 SurpriseDownError : 1;
|
|
UINT32 Reserved2 : 6;
|
|
UINT32 PoisonedTlp : 1;
|
|
UINT32 FlowControlProtocolError : 1;
|
|
UINT32 CompletionTimeout : 1;
|
|
UINT32 CompleterAbort : 1;
|
|
UINT32 UnexpectedCompletion : 1;
|
|
UINT32 ReceiverOverflow : 1;
|
|
UINT32 MalformedTlp : 1;
|
|
UINT32 EcrcError : 1;
|
|
UINT32 UnsupportedRequestError : 1;
|
|
UINT32 AcsVoilation : 1;
|
|
UINT32 UncorrectableInternalError : 1;
|
|
UINT32 McBlockedTlp : 1;
|
|
UINT32 AtomicOpEgressBlocked : 1;
|
|
UINT32 TlpPrefixBlockedError : 1;
|
|
UINT32 Reserved3 : 6;
|
|
} Bits;
|
|
UINT32 Uint32;
|
|
} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
|
|
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
|
|
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
|
|
UINT32 CorrectableErrorStatus;
|
|
UINT32 CorrectableErrorMask;
|
|
UINT32 AdvancedErrorCapabilitiesAndControl;
|
|
UINT32 HeaderLog[4];
|
|
UINT32 RootErrorCommand;
|
|
UINT32 RootErrorStatus;
|
|
UINT16 ErrorSourceIdentification;
|
|
UINT16 CorrectableErrorSourceIdentification;
|
|
UINT32 TlpPrefixLog[4];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
|
|
|
|
typedef struct {
|
|
UINT32 VcResourceCapability:24;
|
|
UINT32 PortArbTableOffset:8;
|
|
UINT32 VcResourceControl;
|
|
UINT16 Reserved1;
|
|
UINT16 VcResourceStatus;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 ExtendedVcCount:3;
|
|
UINT32 PortVcCapability1:29;
|
|
UINT32 PortVcCapability2:24;
|
|
UINT32 VcArbTableOffset:8;
|
|
UINT16 PortVcControl;
|
|
UINT16 PortVcStatus;
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT64 SerialNumber;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 ElementSelfDescription;
|
|
UINT32 Reserved;
|
|
UINT32 LinkEntry[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 RootComplexLinkCapabilities;
|
|
UINT16 RootComplexLinkControl;
|
|
UINT16 RootComplexLinkStatus;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 DataSelect:8;
|
|
UINT32 Reserved:24;
|
|
UINT32 Data;
|
|
UINT32 PowerBudgetCapability:1;
|
|
UINT32 Reserved2:7;
|
|
UINT32 Reserved3:24;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT16 AcsCapability;
|
|
UINT16 AcsControl;
|
|
UINT8 EgressControlVectorArray[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 AssociationBitmap;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
|
|
|
|
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 VendorSpecificHeader;
|
|
UINT8 VendorSpecific[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT16 VendorId;
|
|
UINT16 DeviceId;
|
|
UINT32 RcrbCapabilities;
|
|
UINT32 RcrbControl;
|
|
UINT32 Reserved;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT16 MultiCastCapability;
|
|
UINT16 MulticastControl;
|
|
UINT64 McBaseAddress;
|
|
UINT64 McReceiveAddress;
|
|
UINT64 McBlockAll;
|
|
UINT64 McBlockUntranslated;
|
|
UINT64 McOverlayBar;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
|
|
|
|
typedef struct {
|
|
UINT32 ResizableBarCapability;
|
|
UINT16 ResizableBarControl;
|
|
UINT16 Reserved;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
|
|
|
|
#define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT16 AriCapability;
|
|
UINT16 AriControl;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 DpaCapability;
|
|
UINT32 DpaLatencyIndicator;
|
|
UINT16 DpaStatus;
|
|
UINT16 DpaControl;
|
|
UINT8 DpaPowerAllocationArray[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
|
|
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT16 MaxSnoopLatency;
|
|
UINT16 MaxNoSnoopLatency;
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
|
|
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
|
|
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
|
|
|
|
typedef struct {
|
|
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|
UINT32 TphRequesterCapability;
|
|
UINT32 TphRequesterControl;
|
|
UINT16 TphStTable[1];
|
|
} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
|
|
|
|
#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
|
|
|
|
#pragma pack()
|
|
|
|
#endif
|