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329 lines
6.6 KiB
C
329 lines
6.6 KiB
C
/* $Id: IdeData.h 33027 2010-10-11 06:17:12Z vboxsync $ */
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/** @file
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* IdeData.h
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*/
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/*
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* Copyright (C) 2009-2010 Oracle Corporation
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*
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* This file is part of VirtualBox Open Source Edition (OSE), as
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* available from http://www.virtualbox.org. This file is free software;
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* you can redistribute it and/or modify it under the terms of the GNU
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* General Public License (GPL) as published by the Free Software
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* Foundation, in version 2 as it comes in the "COPYING" file of the
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* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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*/
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/** @file
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Header file for IDE Bus Driver's Data Structures
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Copyright (c) 2006 - 2007 Intel Corporation. <BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _IDE_DATA_H_
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#define _IDE_DATA_H_
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#include <IndustryStandard/Atapi.h>
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//
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// common constants
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//
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#define STALL_1_MILLI_SECOND 1000 // stall 1 ms
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#define STALL_1_SECOND 1000000 // stall 1 second
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typedef enum {
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IdePrimary = 0,
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IdeSecondary = 1,
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IdeMaxChannel = 2
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} EFI_IDE_CHANNEL;
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typedef enum {
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IdeMaster = 0,
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IdeSlave = 1,
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IdeMaxDevice = 2
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} EFI_IDE_DEVICE;
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typedef enum {
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IdeMagnetic, /* ZIP Drive or LS120 Floppy Drive */
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IdeCdRom, /* ATAPI CDROM */
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IdeHardDisk, /* Hard Disk */
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Ide48bitAddressingHardDisk, /* Hard Disk larger than 120GB */
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IdeUnknown
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} IDE_DEVICE_TYPE;
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typedef enum {
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SenseNoSenseKey,
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SenseDeviceNotReadyNoRetry,
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SenseDeviceNotReadyNeedRetry,
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SenseNoMedia,
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SenseMediaChange,
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SenseMediaError,
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SenseOtherSense
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} SENSE_RESULT;
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typedef enum {
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AtaUdmaReadOp,
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AtaUdmaReadExtOp,
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AtaUdmaWriteOp,
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AtaUdmaWriteExtOp
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} ATA_UDMA_OPERATION;
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//
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// IDE Registers
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//
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typedef union {
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UINT16 Command; /* when write */
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UINT16 Status; /* when read */
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} IDE_CMD_OR_STATUS;
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typedef union {
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UINT16 Error; /* when read */
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UINT16 Feature; /* when write */
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} IDE_ERROR_OR_FEATURE;
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typedef union {
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UINT16 AltStatus; /* when read */
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UINT16 DeviceControl; /* when write */
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} IDE_ALTSTATUS_OR_DEVICECONTROL;
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//
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// IDE registers set
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//
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typedef struct {
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UINT16 Data;
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IDE_ERROR_OR_FEATURE Reg1;
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UINT16 SectorCount;
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UINT16 SectorNumber;
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UINT16 CylinderLsb;
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UINT16 CylinderMsb;
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UINT16 Head;
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IDE_CMD_OR_STATUS Reg;
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IDE_ALTSTATUS_OR_DEVICECONTROL Alt;
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UINT16 DriveAddress;
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UINT16 MasterSlave;
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UINT16 BusMasterBaseAddr;
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} IDE_BASE_REGISTERS;
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//
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// IDE registers' base addresses
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//
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typedef struct {
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UINT16 CommandBlockBaseAddr;
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UINT16 ControlBlockBaseAddr;
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UINT16 BusMasterBaseAddr;
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} IDE_REGISTERS_BASE_ADDR;
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//
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// Bit definitions in Programming Interface byte of the Class Code field
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// in PCI IDE controller's Configuration Space
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//
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#define IDE_PRIMARY_OPERATING_MODE BIT0
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#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
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#define IDE_SECONDARY_OPERATING_MODE BIT2
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#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
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//
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// Bus Master Reg
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//
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#define BMIC_NREAD BIT3
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#define BMIC_START BIT0
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#define BMIS_INTERRUPT BIT2
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#define BMIS_ERROR BIT1
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#define BMICP_OFFSET 0x00
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#define BMISP_OFFSET 0x02
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#define BMIDP_OFFSET 0x04
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#define BMICS_OFFSET 0x08
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#define BMISS_OFFSET 0x0A
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#define BMIDS_OFFSET 0x0C
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//
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// Time Out Value For IDE Device Polling
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//
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//
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// ATATIMEOUT is used for waiting time out for ATA device
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//
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//
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// 1 second
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//
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#define ATATIMEOUT 1000
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//
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// ATAPITIMEOUT is used for waiting operation
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// except read and write time out for ATAPI device
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//
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//
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// 1 second
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//
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#define ATAPITIMEOUT 1000
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//
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// ATAPILONGTIMEOUT is used for waiting read and
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// write operation timeout for ATAPI device
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//
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//
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// 2 seconds
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//
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#define CDROMLONGTIMEOUT 2000
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//
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// 5 seconds
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//
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#define ATAPILONGTIMEOUT 5000
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//
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// 10 seconds
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//
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#define ATASMARTTIMEOUT 10000
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//
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// ATAPI6 related data structure definition
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//
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//
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// The maximum sectors count in 28 bit addressing mode
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//
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#define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
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#pragma pack(1)
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typedef struct {
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UINT32 RegionBaseAddr;
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UINT16 ByteCount;
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UINT16 EndOfTable;
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} IDE_DMA_PRD;
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#pragma pack()
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#define SETFEATURE TRUE
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#define CLEARFEATURE FALSE
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///
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/// PIO mode definition
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///
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typedef enum _ATA_PIO_MODE_ {
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AtaPioModeBelow2,
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AtaPioMode2,
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AtaPioMode3,
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AtaPioMode4
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} ATA_PIO_MODE;
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//
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// Multi word DMA definition
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//
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typedef enum _ATA_MDMA_MODE_ {
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AtaMdmaMode0,
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AtaMdmaMode1,
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AtaMdmaMode2
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} ATA_MDMA_MODE;
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//
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// UDMA mode definition
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//
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typedef enum _ATA_UDMA_MODE_ {
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AtaUdmaMode0,
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AtaUdmaMode1,
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AtaUdmaMode2,
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AtaUdmaMode3,
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AtaUdmaMode4,
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AtaUdmaMode5
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} ATA_UDMA_MODE;
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#define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
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#define ATA_MODE_CATEGORY_FLOW_PIO 0x01
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#define ATA_MODE_CATEGORY_MDMA 0x04
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#define ATA_MODE_CATEGORY_UDMA 0x08
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#pragma pack(1)
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typedef struct {
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UINT8 ModeNumber : 3;
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UINT8 ModeCategory : 5;
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} ATA_TRANSFER_MODE;
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typedef struct {
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UINT8 Sector;
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UINT8 Heads;
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UINT8 MultipleSector;
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} ATA_DRIVE_PARMS;
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#pragma pack()
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//
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// IORDY Sample Point field value
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//
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#define ISP_5_CLK 0
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#define ISP_4_CLK 1
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#define ISP_3_CLK 2
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#define ISP_2_CLK 3
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//
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// Recovery Time field value
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//
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#define RECVY_4_CLK 0
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#define RECVY_3_CLK 1
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#define RECVY_2_CLK 2
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#define RECVY_1_CLK 3
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//
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// Slave IDE Timing Register Enable
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//
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#define SITRE BIT14
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//
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// DMA Timing Enable Only Select 1
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//
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#define DTE1 BIT7
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//
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// Pre-fetch and Posting Enable Select 1
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//
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#define PPE1 BIT6
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//
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// IORDY Sample Point Enable Select 1
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//
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#define IE1 BIT5
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//
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// Fast Timing Bank Drive Select 1
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//
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#define TIME1 BIT4
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//
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// DMA Timing Enable Only Select 0
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//
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#define DTE0 BIT3
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//
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// Pre-fetch and Posting Enable Select 0
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//
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#define PPE0 BIT2
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//
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// IOREY Sample Point Enable Select 0
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//
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#define IE0 BIT1
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//
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// Fast Timing Bank Drive Select 0
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//
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#define TIME0 BIT0
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#endif
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