From 64291b4f5b02d0c5bafbd0ee04866b692acd5adb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20Silva?= Date: Tue, 30 Jan 2024 14:21:47 +0000 Subject: [PATCH] Set SN74HC165's clock_inhibit_pin as optional The use of only 3 pins is mentioned, but the configuration values don't reflect that. Datasheet specifies the pin can be directly connected to ground. The code already expects the pin to not be used: https://github.com/esphome/esphome/blob/ec3162282cd5a2c3455dd7a8669b4f762c481a20/esphome/components/sn74hc165/__init__.py#L35 --- components/sn74hc165.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/components/sn74hc165.rst b/components/sn74hc165.rst index baa3f3263..b2099d033 100644 --- a/components/sn74hc165.rst +++ b/components/sn74hc165.rst @@ -11,6 +11,8 @@ Once configured, you can use any of the 8 pins for your projects. Up-to 256 shif to provide more pins, without using more GPIO pins on the controller. They are linked by connecting pin Q of the closer shift register to the pin QH of the next shift register. +The use of CLK INH pin is optional, as it can be directly connected to ground. + .. code-block:: yaml @@ -41,7 +43,7 @@ Configuration variables: - **data_pin** (**Required**, :ref:`Pin Schema `): Pin connected to SN74HC165 Serial Output (QH) input. - **clock_pin** (**Required**, :ref:`Pin Schema `): Pin connected to SN74HC165 Clock (CLK) pin - **load_pin** (**Required**, :ref:`Pin Schema `): Pin connected to SN74HC165 Load input (SH/LD) pin -- **clock_inhibit_pin** (**Required**, :ref:`Pin Schema `): Pin connected to SN74HC165 Clock Inhibit (CLK INH) pin +- **clock_inhibit_pin** (*Optional*, :ref:`Pin Schema `): Pin connected to SN74HC165 Clock Inhibit (CLK INH) pin - **sr_count** (*Optional*, int): Number of daisy-chained shift registers, up-to 256. Defaults to ``1``.