From dbf50381f1ddbf9ab6a92ca78301f2edced55d03 Mon Sep 17 00:00:00 2001
From: Clyde Stubbs <2366188+clydebarrow@users.noreply.github.com>
Date: Thu, 14 Mar 2024 13:42:54 +1100
Subject: [PATCH] SPI: Revert clk_pin to standard output pin schema (#6368)

---
 esphome/components/spi/__init__.py          | 17 ++---------------
 tests/components/spi/test.esp32-s3-idf.yaml |  3 ++-
 2 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/esphome/components/spi/__init__.py b/esphome/components/spi/__init__.py
index c2335bd92a..2847c5bfa1 100644
--- a/esphome/components/spi/__init__.py
+++ b/esphome/components/spi/__init__.py
@@ -29,7 +29,6 @@ from esphome.const import (
     PLATFORM_ESP32,
     PLATFORM_ESP8266,
     PLATFORM_RP2040,
-    CONF_ALLOW_OTHER_USES,
     CONF_DATA_PINS,
 )
 from esphome.core import (
@@ -199,8 +198,6 @@ def get_hw_spi(config, available):
 def validate_spi_config(config):
     available = list(range(len(get_hw_interface_list())))
     for spi in config:
-        # map pin number to schema
-        spi[CONF_CLK_PIN] = pins.gpio_output_pin_schema(spi[CONF_CLK_PIN])
         interface = spi[CONF_INTERFACE]
         if interface == "software":
             pass
@@ -257,21 +254,11 @@ def get_spi_interface(index):
     return "new SPIClass(HSPI)"
 
 
-# Do not use a pin schema for the number, as that will trigger a pin reuse error due to duplication of the
-# clock pin in the standard and quad schemas.
-clk_pin_validator = cv.maybe_simple_value(
-    {
-        cv.Required(CONF_NUMBER): cv.Any(cv.int_, cv.string),
-        cv.Optional(CONF_ALLOW_OTHER_USES): cv.boolean,
-    },
-    key=CONF_NUMBER,
-)
-
 SPI_SCHEMA = cv.All(
     cv.Schema(
         {
             cv.GenerateID(): cv.declare_id(SPIComponent),
-            cv.Required(CONF_CLK_PIN): clk_pin_validator,
+            cv.Required(CONF_CLK_PIN): pins.gpio_output_pin_schema,
             cv.Optional(CONF_MISO_PIN): pins.gpio_input_pin_schema,
             cv.Optional(CONF_MOSI_PIN): pins.gpio_output_pin_schema,
             cv.Optional(CONF_FORCE_SW): cv.invalid(
@@ -291,7 +278,7 @@ SPI_QUAD_SCHEMA = cv.All(
     cv.Schema(
         {
             cv.GenerateID(): cv.declare_id(QuadSPIComponent),
-            cv.Required(CONF_CLK_PIN): clk_pin_validator,
+            cv.Required(CONF_CLK_PIN): pins.gpio_output_pin_schema,
             cv.Required(CONF_DATA_PINS): cv.All(
                 cv.ensure_list(pins.internal_gpio_output_pin_number),
                 cv.Length(min=4, max=4),
diff --git a/tests/components/spi/test.esp32-s3-idf.yaml b/tests/components/spi/test.esp32-s3-idf.yaml
index 3aae21cbeb..8db934023a 100644
--- a/tests/components/spi/test.esp32-s3-idf.yaml
+++ b/tests/components/spi/test.esp32-s3-idf.yaml
@@ -2,7 +2,8 @@ spi:
   - id: spi_id_1
     type: single
     clk_pin:
-      number: GPIO7
+      number: GPIO0
+      ignore_strapping_warning: true
       allow_other_uses: false
     mosi_pin: GPIO6
     interface: hardware