2020-04-16 11:09:22 +02:00
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/*
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* Pci.h
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*
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* Created on: 16 Apr 2020
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* Author: jief
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*/
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#ifndef INCLUDE_PCI_H_
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#define INCLUDE_PCI_H_
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2021-05-05 19:10:10 +02:00
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#include <stdint.h>
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2021-09-28 10:28:45 +02:00
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#include "../cpp_foundation/XBool.h"
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2020-04-16 11:09:22 +02:00
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/* PCI */
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#define PCI_CLASS_MEDIA_HDA 0x03
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#define PCIADDR(bus, dev, func) ((1 << 31) | ((bus) << 16) | ((dev) << 11) | ((func) << 8))
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typedef struct {
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2021-05-05 19:10:10 +02:00
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uint32_t :2;
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uint32_t reg :6;
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uint32_t func:3;
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uint32_t dev :5;
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uint32_t bus :8;
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uint32_t :7;
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uint32_t eb :1;
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2020-04-16 11:09:22 +02:00
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} pci_addr_t;
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2021-10-03 19:33:03 +02:00
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typedef union pci_dev_t {
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uint32_t addr = 0;
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2020-04-16 11:09:22 +02:00
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pci_addr_t bits;
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} pci_dev_t;
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typedef struct pci_dt_t {
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// EFI_PCI_IO_PROTOCOL *PciIo;
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// PCI_TYPE00 Pci;
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2021-09-28 10:28:45 +02:00
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EFI_HANDLE DeviceHandle = NULL;
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UINT8* regs = NULL;
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pci_dev_t dev = pci_dev_t();
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2020-04-16 11:09:22 +02:00
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2021-09-28 10:28:45 +02:00
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UINT16 vendor_id = 0;
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UINT16 device_id = 0;
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2020-04-16 11:09:22 +02:00
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union {
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struct {
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UINT16 vendor_id;
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UINT16 device_id;
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} subsys;
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UINT32 subsys_id;
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} subsys_id_union = { {0, 0} };
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UINT8 revision = 0;
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UINT8 subclass = 0;
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UINT16 class_id = 0;
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2020-04-16 11:09:22 +02:00
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2021-09-28 10:28:45 +02:00
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struct pci_dt_t *parent = NULL;
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struct pci_dt_t *children = NULL;
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struct pci_dt_t *next = NULL;
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2021-09-28 15:54:31 +02:00
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XBool used = false;
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2020-04-16 11:09:22 +02:00
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} pci_dt_t;
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2022-07-28 19:46:19 +02:00
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#if 0
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//
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// Definitions of PCI class bytes and manipulation macros.
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//
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#define PCI_CLASS_OLD 0x00
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#define PCI_CLASS_OLD_OTHER 0x00
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#define PCI_CLASS_OLD_VGA 0x01
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
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#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
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#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
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#define PCI_CLASS_MASS_STORAGE_IDE 0x01
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#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
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#define PCI_CLASS_MASS_STORAGE_IPI 0x03
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#define PCI_CLASS_MASS_STORAGE_RAID 0x04
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#define PCI_CLASS_MASS_STORAGE_ATA 0x05
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#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20
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#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30
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#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
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#define PCI_IF_MASS_STORAGE_SATA 0x00
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#define PCI_IF_MASS_STORAGE_AHCI 0x01
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#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
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#define PCI_CLASS_MASS_STORAGE_SAS 0x07
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#define PCI_IF_MASS_STORAGE_SAS 0x00
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#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
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#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
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#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
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#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
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#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
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#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
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#define PCI_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x00
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#define PCI_CLASS_NETWORK_TOKENRING 0x01
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#define PCI_CLASS_NETWORK_FDDI 0x02
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#define PCI_CLASS_NETWORK_ATM 0x03
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#define PCI_CLASS_NETWORK_ISDN 0x04
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#define PCI_CLASS_NETWORK_WORLDFIP 0x05
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#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
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#define PCI_CLASS_NETWORK_INFINIBAND 0x07
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#define PCI_CLASS_NETWORK_OTHER 0x80
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#define PCI_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_VGA 0x00
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#define PCI_IF_VGA_VGA 0x00
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#define PCI_IF_VGA_8514 0x01
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#define PCI_CLASS_DISPLAY_XGA 0x01
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#define PCI_CLASS_DISPLAY_3D 0x02
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#define PCI_CLASS_DISPLAY_OTHER 0x80
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#define PCI_CLASS_MEDIA 0x04
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#define PCI_CLASS_MEDIA_VIDEO 0x00
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#define PCI_CLASS_MEDIA_AUDIO 0x01
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#define PCI_CLASS_MEDIA_TELEPHONE 0x02
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#define PCI_CLASS_MEDIA_HDA 0x03
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#define PCI_CLASS_MEDIA_MIXED_MODE 0x03 //other name
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#define PCI_CLASS_MEDIA_OTHER 0x80
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#define PCI_CLASS_MEMORY_CONTROLLER 0x05
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#define PCI_CLASS_MEMORY_RAM 0x00
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#define PCI_CLASS_MEMORY_FLASH 0x01
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#define PCI_CLASS_MEMORY_OTHER 0x80
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x00
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#define PCI_CLASS_BRIDGE_ISA 0x01
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#define PCI_CLASS_BRIDGE_EISA 0x02
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#define PCI_CLASS_BRIDGE_MCA 0x03
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#define PCI_CLASS_BRIDGE_P2P 0x04
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#define PCI_IF_BRIDGE_P2P 0x00
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#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
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#define PCI_CLASS_BRIDGE_PCMCIA 0x05
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#define PCI_CLASS_BRIDGE_NUBUS 0x06
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#define PCI_CLASS_BRIDGE_CARDBUS 0x07
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#define PCI_CLASS_BRIDGE_RACEWAY 0x08
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#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
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#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
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#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
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#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
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#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
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#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
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#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
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#define PCI_CLASS_BRIDGE_OTHER 0x80
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#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
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#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
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#define PCI_SUBCLASS_SERIAL 0x00
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#define PCI_IF_GENERIC_XT 0x00
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#define PCI_IF_16450 0x01
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#define PCI_IF_16550 0x02
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#define PCI_IF_16650 0x03
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#define PCI_IF_16750 0x04
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#define PCI_IF_16850 0x05
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#define PCI_IF_16950 0x06
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#define PCI_SUBCLASS_PARALLEL 0x01
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#define PCI_IF_PARALLEL_PORT 0x00
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#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
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#define PCI_IF_ECP_PARALLEL_PORT 0x02
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#define PCI_IF_1284_CONTROLLER 0x03
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#define PCI_IF_1284_DEVICE 0xFE
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#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
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#define PCI_SUBCLASS_MODEM 0x03
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#define PCI_IF_GENERIC_MODEM 0x00
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#define PCI_IF_16450_MODEM 0x01
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#define PCI_IF_16550_MODEM 0x02
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#define PCI_IF_16650_MODEM 0x03
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#define PCI_IF_16750_MODEM 0x04
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#define PCI_SUBCLASS_GPIB 0x04
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#define PCI_SUBCLASS_SMART_CARD 0x05
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#define PCI_SUBCLASS_SCC_OTHER 0x80
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#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
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#define PCI_SUBCLASS_PIC 0x00
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#define PCI_IF_8259_PIC 0x00
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#define PCI_IF_ISA_PIC 0x01
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#define PCI_IF_EISA_PIC 0x02
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#define PCI_IF_HPET 0x03
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#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
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#define PCI_IF_APIC_CONTROLLER2 0x20
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#define PCI_SUBCLASS_DMA 0x01
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#define PCI_IF_8237_DMA 0x00
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#define PCI_IF_ISA_DMA 0x01
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#define PCI_IF_EISA_DMA 0x02
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#define PCI_SUBCLASS_TIMER 0x02
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#define PCI_IF_8254_TIMER 0x00
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#define PCI_IF_ISA_TIMER 0x01
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#define PCI_IF_EISA_TIMER 0x02
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#define PCI_SUBCLASS_RTC 0x03
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#define PCI_IF_GENERIC_RTC 0x00
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#define PCI_IF_ISA_RTC 0x01
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#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
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#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
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#define PCI_SUBCLASS_IOMMU 0x06
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#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
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#define PCI_CLASS_INPUT_DEVICE 0x09
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#define PCI_SUBCLASS_KEYBOARD 0x00
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#define PCI_SUBCLASS_PEN 0x01
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#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
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#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
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#define PCI_SUBCLASS_GAMEPORT 0x04
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#define PCI_IF_GAMEPORT 0x00
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#define PCI_IF_GAMEPORT1 0x10
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#define PCI_SUBCLASS_INPUT_OTHER 0x80
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#define PCI_CLASS_DOCKING_STATION 0x0A
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#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
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#define PCI_SUBCLASS_DOCKING_OTHER 0x80
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#define PCI_CLASS_PROCESSOR 0x0B
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#define PCI_SUBCLASS_PROC_386 0x00
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#define PCI_SUBCLASS_PROC_486 0x01
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#define PCI_SUBCLASS_PROC_PENTIUM 0x02
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#define PCI_SUBCLASS_PROC_ALPHA 0x10
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#define PCI_SUBCLASS_PROC_POWERPC 0x20
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#define PCI_SUBCLASS_PROC_MIPS 0x30
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#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
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#define PCI_SUBCLASS_PROC_OTHER 0x80
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#define PCI_CLASS_SERIAL 0x0C
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#define PCI_CLASS_SERIAL_FIREWIRE 0x00
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#define PCI_IF_1394 0x00
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#define PCI_IF_1394_OPEN_HCI 0x10
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#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
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#define PCI_CLASS_SERIAL_SSA 0x02
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#define PCI_CLASS_SERIAL_USB 0x03
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#define PCI_IF_UHCI 0x00
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#define PCI_IF_OHCI 0x10
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#define PCI_IF_EHCI 0x20
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#define PCI_IF_XHCI 0x30
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#define PCI_IF_USB_OTHER 0x80
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#define PCI_IF_USB_DEVICE 0xFE
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#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
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#define PCI_CLASS_SERIAL_SMB 0x05
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#define PCI_CLASS_SERIAL_IB 0x06
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#define PCI_CLASS_SERIAL_IPMI 0x07
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#define PCI_IF_IPMI_SMIC 0x00
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#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
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#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
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#define PCI_CLASS_SERIAL_SERCOS 0x08
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#define PCI_CLASS_SERIAL_CANBUS 0x09
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#define PCI_CLASS_SERIAL_OTHER 0x80
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#define PCI_CLASS_WIRELESS 0x0D
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#define PCI_SUBCLASS_IRDA 0x00
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#define PCI_SUBCLASS_IR 0x01
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#define PCI_SUBCLASS_RF 0x10
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#define PCI_SUBCLASS_BLUETOOTH 0x11
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#define PCI_SUBCLASS_BROADBAND 0x12
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#define PCI_SUBCLASS_ETHERNET_80211A 0x20
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#define PCI_SUBCLASS_ETHERNET_80211B 0x21
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#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
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#define PCI_CLASS_INTELLIGENT_IO 0x0E
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#define PCI_CLASS_SATELLITE 0x0F
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#define PCI_SUBCLASS_TV 0x01
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#define PCI_SUBCLASS_AUDIO 0x02
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#define PCI_SUBCLASS_VOICE 0x03
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#define PCI_SUBCLASS_DATA 0x04
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#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
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#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
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#define PCI_SUBCLASS_NET_COMPUT 0x00
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#define PCI_SUBCLASS_ENTERTAINMENT 0x10
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#define PCI_SUBCLASS_SECURITY_OTHER 0x80
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#define PCI_CLASS_DPIO 0x11
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#define PCI_SUBCLASS_DPIO 0x00
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#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
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#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
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#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
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#define PCI_SUBCLASS_DPIO_OTHER 0x80
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#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
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#endif
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2020-04-16 11:09:22 +02:00
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#endif /* INCLUDE_PCI_H_ */
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