mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-12-26 16:47:40 +01:00
147 lines
4.3 KiB
NASM
147 lines
4.3 KiB
NASM
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SmmInit.nasm
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;
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; Abstract:
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;
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; Functions for relocating SMBASE's for all processors
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;
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;-------------------------------------------------------------------------------
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%include "StuffRsbNasm.inc"
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extern ASM_PFX(SmmInitHandler)
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extern ASM_PFX(mRebasedFlag)
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extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gPatchSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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global ASM_PFX(gPatchRebasedFlagAddr32)
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global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
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%define LONG_MODE_CS 0x38
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DEFAULT REL
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SECTION .text
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ASM_PFX(gcSmiInitGdtr):
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DW 0
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DQ 0
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global ASM_PFX(SmmStartup)
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BITS 16
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ASM_PFX(SmmStartup):
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mov eax, 0x80000001 ; read capability
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cpuid
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr3):
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mov cr3, eax
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o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr4):
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or ah, 2 ; enable XMM registers access
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mov cr4, eax
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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or ah, BIT0 ; set LME bit
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test ebx, BIT20 ; check NXE capability
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jz .1
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or ah, BIT3 ; set NXE bit
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.1:
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wrmsr
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr0):
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mov cr0, eax ; enable protected mode & paging
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jmp LONG_MODE_CS : dword 0 ; offset will be patched to @LongMode
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@PatchLongModeOffset:
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BITS 64
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@LongMode: ; long-mode starts here
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mov rsp, strict qword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmInitStack):
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and sp, 0xfff0 ; make sure RSP is 16-byte aligned
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;
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; According to X64 calling convention, XMM0~5 are volatile, we need to save
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; them before calling C-function.
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;
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sub rsp, 0x60
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movdqa [rsp], xmm0
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movdqa [rsp + 0x10], xmm1
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movdqa [rsp + 0x20], xmm2
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movdqa [rsp + 0x30], xmm3
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movdqa [rsp + 0x40], xmm4
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movdqa [rsp + 0x50], xmm5
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add rsp, -0x20
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call ASM_PFX(SmmInitHandler)
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add rsp, 0x20
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;
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; Restore XMM0~5 after calling C-function.
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;
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movdqa xmm0, [rsp]
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movdqa xmm1, [rsp + 0x10]
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movdqa xmm2, [rsp + 0x20]
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movdqa xmm3, [rsp + 0x30]
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movdqa xmm4, [rsp + 0x40]
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movdqa xmm5, [rsp + 0x50]
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StuffRsb64
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rsm
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BITS 16
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ASM_PFX(gcSmmInitTemplate):
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mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
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sub ebp, 0x30000
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jmp ebp
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@L1:
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DQ 0; ASM_PFX(SmmStartup)
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ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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BITS 64
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global ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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push rax
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mov rax, [ASM_PFX(mRebasedFlag)]
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mov byte [rax], 1
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pop rax
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jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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;
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; Semaphore code running in 32-bit mode
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;
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BITS 32
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global ASM_PFX(SmmRelocationSemaphoreComplete32)
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ASM_PFX(SmmRelocationSemaphoreComplete32):
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push eax
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchRebasedFlagAddr32):
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mov byte [eax], 1
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pop eax
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jmp dword [dword 0] ; destination will be patched
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ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
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BITS 64
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global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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lea rax, [@LongMode]
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lea rcx, [@PatchLongModeOffset - 6]
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mov dword [rcx], eax
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lea rax, [ASM_PFX(SmmStartup)]
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lea rcx, [@L1]
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mov qword [rcx], rax
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ret
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