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1st experiment to use OpenCore to boot Big Sur installer.

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This commit is contained in:
jief666 2020-09-07 01:19:48 +03:00
parent f4e10b1a2a
commit 8ccee7054f
711 changed files with 63004 additions and 149300 deletions
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3
.gitmodules vendored Normal file
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@ -0,0 +1,3 @@
[submodule "OpenCorePkg"]
path = OpenCorePkg
url = https://github.com/CloverHackyColor/OpenCorePkg.git

119
Clover.dsc
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@ -88,7 +88,7 @@
#EblCmdLib|EmbeddedPkg/Library/EblCmdLibNull/EblCmdLibNull.inf
FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
UefiCpuLib|CloverEFI/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
!ifdef ENABLE_SECURE_BOOT
OpensslLib|Library/OpensslLib/openssl-$(OPENSSL_VERSION)/OpensslLib.inf
IntrinsicLib|Library/IntrinsicLib/IntrinsicLib.inf
@ -134,11 +134,11 @@
PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
#SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
MtrrLib|CloverEFI/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
#SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
LocalApicLib|CloverEFI/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
#LocalApicLib|CloverEFI/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
#LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
#
# To save size, use NULL library for DebugLib and ReportStatusCodeLib.
@ -147,11 +147,13 @@
!ifdef DEBUG_ON_SERIAL_PORT
BaseSerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
!else
BaseSerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
SerialPortLib|MdeModulePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
!endif
BaseDebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
DebugLib|OpenCorePkg/Library/OcDebugLogLib/OcDebugLogLib.inf
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
@ -170,35 +172,64 @@
#
# OC libs
#
OcGuardLib|Library/OcGuardLib/OcGuardLib.inf
OcAfterBootCompatLib|Library/OcAfterBootCompatLib/OcAfterBootCompatLib.inf
OcAppleBootPolicyLib|Library/OcAppleBootPolicyLib/OcAppleBootPolicyLib.inf
OcAppleChunklistLib|Library/OcAppleChunklistLib/OcAppleChunklistLib.inf
OcAppleDiskImageLib|Library/OcAppleDiskImageLib/OcAppleDiskImageLib.inf
OcAppleKeyMapLib|Library/OcAppleKeyMapLib/OcAppleKeyMapLib.inf
OcAppleKeysLib|Library/OcAppleKeysLib/OcAppleKeysLib.inf
OcAppleRamDiskLib|Library/OcAppleRamDiskLib/OcAppleRamDiskLib.inf
OcBootManagementLib|Library/OcBootManagementLib/OcBootManagementLib.inf
OcCompressionLib|Library/OcCompressionLib/OcCompressionLib.inf
OcConsoleLib|Library/OcConsoleLib/OcConsoleLib.inf
OcCpuLib|Library/OcCpuLib/OcCpuLib.inf
OcCryptoLib|Library/OcCryptoLib/OcCryptoLib.inf
OcDebugLogLib|Library/OcDebugLogLib/OcDebugLogLib.inf
OcDevicePathLib|Library/OcDevicePathLib/OcDevicePathLib.inf
OcFileLib|Library/OcFileLib/OcFileLib.inf
OcMemoryLib|Library/OcMemoryLib/OcMemoryLib.inf
OcMiscLib|Library/OcMiscLib/OcMiscLib.inf
OcOSInfoLib|Library/OcOSInfoLib/OcOSInfoLib.inf
OcRngLib|Library/OcRngLib/OcRngLib.inf
OcRtcLib|Library/OcRtcLib/OcRtcLib.inf
OcSerializeLib|Library/OcSerializeLib/OcSerializeLib.inf
OcStringLib|Library/OcStringLib/OcStringLib.inf
OcStorageLib|Library/OcStorageLib/OcStorageLib.inf
OcTemplateLib|Library/OcTemplateLib/OcTemplateLib.inf
OcXmlLib|Library/OcXmlLib/OcXmlLib.inf
OcGuardLib|OpenCorePkg/Library/OcGuardLib/OcGuardLib.inf
OcAfterBootCompatLib|OpenCorePkg/Library/OcAfterBootCompatLib/OcAfterBootCompatLib.inf
OcAppleBootPolicyLib|OpenCorePkg/Library/OcAppleBootPolicyLib/OcAppleBootPolicyLib.inf
OcAppleChunklistLib|OpenCorePkg/Library/OcAppleChunklistLib/OcAppleChunklistLib.inf
OcAppleDiskImageLib|OpenCorePkg/Library/OcAppleDiskImageLib/OcAppleDiskImageLib.inf
OcAppleKeyMapLib|OpenCorePkg/Library/OcAppleKeyMapLib/OcAppleKeyMapLib.inf
OcAppleKeysLib|OpenCorePkg/Library/OcAppleKeysLib/OcAppleKeysLib.inf
OcAppleRamDiskLib|OpenCorePkg/Library/OcAppleRamDiskLib/OcAppleRamDiskLib.inf
OcBootManagementLib|OpenCorePkg/Library/OcBootManagementLib/OcBootManagementLib.inf
OcCompressionLib|OpenCorePkg/Library/OcCompressionLib/OcCompressionLib.inf
OcConsoleLib|OpenCorePkg/Library/OcConsoleLib/OcConsoleLib.inf
OcCpuLib|OpenCorePkg/Library/OcCpuLib/OcCpuLib.inf
OcCryptoLib|OpenCorePkg/Library/OcCryptoLib/OcCryptoLib.inf
OcDebugLogLib|OpenCorePkg/Library/OcDebugLogLib/OcDebugLogLib.inf
OcDevicePathLib|OpenCorePkg/Library/OcDevicePathLib/OcDevicePathLib.inf
OcFileLib|OpenCorePkg/Library/OcFileLib/OcFileLib.inf
OcMemoryLib|OpenCorePkg/Library/OcMemoryLib/OcMemoryLib.inf
OcMiscLib|OpenCorePkg/Library/OcMiscLib/OcMiscLib.inf
OcOSInfoLib|OpenCorePkg/Library/OcOSInfoLib/OcOSInfoLib.inf
OcRngLib|OpenCorePkg/Library/OcRngLib/OcRngLib.inf
OcRtcLib|OpenCorePkg/Library/OcRtcLib/OcRtcLib.inf
OcSerializeLib|OpenCorePkg/Library/OcSerializeLib/OcSerializeLib.inf
OcStringLib|OpenCorePkg/Library/OcStringLib/OcStringLib.inf
OcStorageLib|OpenCorePkg/Library/OcStorageLib/OcStorageLib.inf
OcTemplateLib|OpenCorePkg/Library/OcTemplateLib/OcTemplateLib.inf
OcXmlLib|OpenCorePkg/Library/OcXmlLib/OcXmlLib.inf
OcDeviceTreeLib|OpenCorePkg/Library/OcDeviceTreeLib/OcDeviceTreeLib.inf
OcDebugLogLib|OpenCorePkg/Library/OcDebugLogLib/OcDebugLogLib.inf
OcDataHubLib|OpenCorePkg/Library/OcDataHubLib/OcDataHubLib.inf
OcAppleImg4Lib|OpenCorePkg/Library/OcAppleImg4Lib/OcAppleImg4Lib.inf
OcAppleKernelLib|OpenCorePkg/Library/OcAppleKernelLib/OcAppleKernelLib.inf
OcMachoLib|OpenCorePkg/Library/OcMachoLib/OcMachoLib.inf
OcVirtualFsLib|OpenCorePkg/Library/OcVirtualFsLib/OcVirtualFsLib.inf
OcMacInfoLib|OpenCorePkg/Library/OcMacInfoLib/OcMacInfoLib.inf
OcApfsLib|OpenCorePkg/Library/OcApfsLib/OcApfsLib.inf
OcAppleSecureBootLib|OpenCorePkg/Library/OcAppleSecureBootLib/OcAppleSecureBootLib.inf
OcAppleImageVerificationLib|OpenCorePkg/Library/OcAppleImageVerificationLib/OcAppleImageVerificationLib.inf
OcDriverConnectionLib|OpenCorePkg/Library/OcDriverConnectionLib/OcDriverConnectionLib.inf
OcDebugLogLib|OpenCorePkg/Library/OcDebugLogLib/OcDebugLogLib.inf
OcAcpiLib|OpenCorePkg/Library/OcAcpiLib/OcAcpiLib.inf
OcAppleEventLib|OpenCorePkg/Library/OcAppleEventLib/OcAppleEventLib.inf
#OcAppleImageConversionLib|OpenCorePkg/Library/OcAppleImageConversionLib/OcAppleImageConversionLib.inf
OcAudioLib|OpenCorePkg/Library/OcAudioLib/OcAudioLib.inf
OcInputLib|OpenCorePkg/Library/OcInputLib/OcInputLib.inf
OcAppleUserInterfaceThemeLib|OpenCorePkg/Library/OcAppleUserInterfaceThemeLib/OcAppleUserInterfaceThemeLib.inf
OcConfigurationLib|OpenCorePkg/Library/OcConfigurationLib/OcConfigurationLib.inf
OcDevicePropertyLib|OpenCorePkg/Library/OcDevicePropertyLib/OcDevicePropertyLib.inf
OcFirmwareVolumeLib|OpenCorePkg/Library/OcFirmwareVolumeLib/OcFirmwareVolumeLib.inf
OcHashServicesLib|OpenCorePkg/Library/OcHashServicesLib/OcHashServicesLib.inf
OcSmbiosLib|OpenCorePkg/Library/OcSmbiosLib/OcSmbiosLib.inf
OcSmcLib|OpenCorePkg/Library/OcSmcLib/OcSmcLib.inf
OcUnicodeCollationEngGenericLib|OpenCorePkg/Library/OcUnicodeCollationEngLib/OcUnicodeCollationEngGenericLib.inf
OcPeCoffLib|OpenCorePkg/Library/OcPeCoffLib/OcPeCoffLib.inf
#OcPngLib|OpenCorePkg/Library/OcPngLib/OcPngLib.inf
OpenCoreLib|OpenCorePkg/Platform/OpenCore/OpenCoreLib.inf
MachoLib|Library/MachoLib/MachoLib.inf
DeviceTreeLib|Library/DeviceTreeLib/DeviceTreeLib.inf
#MachoLib|Library/MachoLib/MachoLib.inf
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
@ -353,7 +384,7 @@
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
CloverEFI/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
#UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
#UefiCpuPkg/CpuDxe/CpuDxe.inf
#UefiCpuPkg/CpuDxe/CpuDxe.inf
@ -489,7 +520,7 @@
#MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf
#MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
#SaveResume/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
#CloverEFI/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
#UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
# Bios Thunk
#IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/VideoDxe.inf
@ -610,7 +641,7 @@
<LibraryClasses>
SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
}
!else
rEFIt_UEFI/refit.inf {
@ -626,8 +657,8 @@
MemoryFix/OsxAptioFixDrv/OsxAptioFix3Drv.inf
MemoryFix/OsxLowMemFixDrv/OsxLowMemFixDrv.inf
MemoryFix/AptioMemoryFix/AptioMemoryFix.inf
MemoryFix/OpenRuntime/OpenRuntime.inf
MemoryFix/OcQuirks/OcQuirks.inf
OpenCorePkg/Platform/OpenRuntime/OpenRuntime.inf
!ifdef DEBUG_ON_SERIAL_PORT
MemoryFix/OsxAptioFixDrv/OsxAptioFixDrv.inf {
#
@ -714,14 +745,14 @@ DEFINE EXIT_USBKB_FLAG = -DEXIT_USBKB
!endif
DEFINE BUILD_OPTIONS=-DMDEPKG_NDEBUG -DCLOVER_BUILD $(VBIOS_PATCH_CLOVEREFI_FLAG) $(ONLY_SATA_0_FLAG) $(BLOCKIO_FLAG) $(NOUSB_FLAG) $(NOUDMA_FLAG) $(AMD_FLAG) $(SECURE_BOOT_FLAG) $(ANDX86_FLAG) $(PS2MOUSE_LEGACYBOOT_FLAG) $(DEBUG_ON_SERIAL_PORT_FLAG) $(EXIT_USBKB_FLAG)
DEFINE BUILD_OPTIONS=-DCLOVER_BUILD $(VBIOS_PATCH_CLOVEREFI_FLAG) $(ONLY_SATA_0_FLAG) $(BLOCKIO_FLAG) $(NOUSB_FLAG) $(NOUDMA_FLAG) $(AMD_FLAG) $(SECURE_BOOT_FLAG) $(ANDX86_FLAG) $(PS2MOUSE_LEGACYBOOT_FLAG) $(DEBUG_ON_SERIAL_PORT_FLAG) $(EXIT_USBKB_FLAG)
#MSFT:*_*_*_CC_FLAGS = /FAcs /FR$(@R).SBR /wd4701 /wd4703 $(BUILD_OPTIONS)
MSFT:*_*_*_CC_FLAGS = /FAcs $(BUILD_OPTIONS) -Dinline=__inline /Zi -D DISABLE_NEW_DEPRECATED_INTERFACES
MSFT:*_*_*_CC_FLAGS = /FAcs $(BUILD_OPTIONS) -Dinline=__inline /Zi -D DISABLE_NEW_DEPRECATED_INTERFACES -D OC_TARGET_DEBUG
XCODE:*_*_*_CC_FLAGS = -fno-unwind-tables -Wno-msvc-include -Os $(BUILD_OPTIONS) $(DISABLE_LTO_FLAG) -D DISABLE_NEW_DEPRECATED_INTERFACES
GCC:*_*_*_CC_FLAGS = $(BUILD_OPTIONS) $(DISABLE_LTO_FLAG) -D DISABLE_NEW_DEPRECATED_INTERFACES
GCC:*_*_*_CXX_FLAGS = $(BUILD_OPTIONS) $(DISABLE_LTO_FLAG) -D DISABLE_NEW_DEPRECATED_INTERFACES
XCODE:*_*_*_CC_FLAGS = -fno-unwind-tables -Wno-msvc-include -Os $(BUILD_OPTIONS) $(DISABLE_LTO_FLAG) -D DISABLE_NEW_DEPRECATED_INTERFACES -D OC_TARGET_DEBUG
GCC:*_*_*_CC_FLAGS = $(BUILD_OPTIONS) $(DISABLE_LTO_FLAG) -D DISABLE_NEW_DEPRECATED_INTERFACES -D OC_TARGET_DEBUG
GCC:*_*_*_CXX_FLAGS = $(BUILD_OPTIONS) $(DISABLE_LTO_FLAG) -D DISABLE_NEW_DEPRECATED_INTERFACES -D OC_TARGET_DEBUG
#-fanalyzer -Wmismatched-tags
#-Weffc++
#-Wunused-but-set-variable

2
Clover.fdf
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@ -104,7 +104,7 @@ INF CloverEFI/OsxSmbiosGenDxe/SmbiosGen.inf
INF CloverEFI/OsxBdsDxe/BdsDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF CloverEFI/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
#INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
#INF UefiCpuPkg/CpuDxe/CpuDxe.inf
#INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf

12
CloverEFI/BiosKeyboard/BiosKeyboard.c
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@ -37,7 +37,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define DBG(...)
#endif
extern int MapBiosKey(EFI_KEY_DATA KeyData, APPLE_KEY* pKey, UINT8* pCurModifierMap);
extern int MapBiosKey(EFI_KEY_DATA KeyData, APPLE_KEY_CODE* pKey, UINT8* pCurModifierMap);
//
// EFI Driver Binding Protocol Instance
//
@ -1840,7 +1840,7 @@ CheckKeyboardConnect (
**/
static int apple_need_zero = 0;
int MapBiosKey(EFI_KEY_DATA KeyData, APPLE_KEY* pKey, UINT8* pCurModifierMap)
int MapBiosKey(EFI_KEY_DATA KeyData, APPLE_KEY_CODE* pKey, UINT8* pCurModifierMap)
{
if ( KeyData.Key.UnicodeChar == 0 )
{
@ -2045,7 +2045,7 @@ BiosKeyboardTimerHandler (
BIOS_KEYBOARD_CONSOLE_IN_EX_NOTIFY *CurrentNotify;
//for AppleDb
UINTN NumberOfKeys;
APPLE_KEY Keys[8]; // APPLE_KEY is UINT16
APPLE_KEY_CODE Keys[8]; // APPLE_KEY_CODE is UINT16
ZeroMem (&Regs, sizeof (EFI_IA32_REGISTER_SET));
@ -2310,9 +2310,9 @@ BiosKeyboardTimerHandler (
*/
// NumberOfKeys = 3;
// Keys[0] = (APPLE_KEY)KeyData.KeyState.KeyShiftState;
// Keys[1] = (APPLE_KEY)KeyData.KeyState.KeyToggleState; //or 0?
// Keys[2] = (APPLE_KEY)KeyData.Key.ScanCode;
// Keys[0] = (APPLE_KEY_CODE)KeyData.KeyState.KeyShiftState;
// Keys[1] = (APPLE_KEY_CODE)KeyData.KeyState.KeyToggleState; //or 0?
// Keys[2] = (APPLE_KEY_CODE)KeyData.Key.ScanCode;
// Parse the modifier key, which is the first byte of keyboard input report.
//

70
CloverEFI/UefiCpuPkg/CpuDxe/CpuDxe.inf
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@ -1,70 +0,0 @@
## @file
#
# Component description file for simple CPU driver
#
# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CpuDxeClover
FILE_GUID = 1A1E4886-9517-440e-9FDE-3BE44CEE2136
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InitializeCpu
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
CpuLib
DebugLib
DxeServicesTableLib
MemoryAllocationLib
MtrrLib
UefiBootServicesTableLib
UefiDriverEntryPoint
LocalApicLib
UefiCpuLib
[Sources]
CpuDxe.c
CpuDxe.h
CpuGdt.c
Ia32/IvtAsm.asm | MSFT
Ia32/IvtAsm.asm | INTEL
Ia32/IvtAsm.S | GCC
[Sources.IA32]
Ia32/CpuAsm.asm | MSFT
Ia32/CpuAsm.asm | INTEL
Ia32/CpuAsm.S | GCC
[Sources.X64]
X64/CpuAsm.asm | MSFT
X64/CpuAsm.asm | INTEL
X64/CpuAsm.S | GCC
[Protocols]
gEfiCpuArchProtocolGuid
[Guids]
gIdleLoopEventGuid ## CONSUMES ## GUID
[Depex]
TRUE

201
CloverEFI/UefiCpuPkg/CpuDxe/CpuGdt.c
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@ -1,201 +0,0 @@
/** @file
C based implemention of IA32 interrupt handling only
requiring a minimal assembly interrupt entry point.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuDxe.h"
//
// Local structure definitions
//
#pragma pack (1)
//
// Global Descriptor Entry structures
//
typedef struct _GDT_ENTRY {
UINT16 Limit15_0;
UINT16 Base15_0;
UINT8 Base23_16;
UINT8 Type;
UINT8 Limit19_16_and_flags;
UINT8 Base31_24;
} GDT_ENTRY;
typedef
struct _GDT_ENTRIES {
GDT_ENTRY Null;
GDT_ENTRY Linear;
GDT_ENTRY LinearCode;
GDT_ENTRY SysData;
GDT_ENTRY SysCode;
GDT_ENTRY LinearCode64;
GDT_ENTRY Spare4;
GDT_ENTRY Spare5;
} GDT_ENTRIES;
#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)
#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)
#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)
#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)
#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)
#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)
#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)
#if defined (MDE_CPU_IA32)
#define CPU_CODE_SEL LINEAR_CODE_SEL
#define CPU_DATA_SEL LINEAR_SEL
#elif defined (MDE_CPU_X64)
#define CPU_CODE_SEL LINEAR_CODE64_SEL
#define CPU_DATA_SEL LINEAR_SEL
//#else
//#error CPU type not supported for CPU GDT initialization!
#endif
//
// Global descriptor table (GDT) Template
//
STATIC GDT_ENTRIES GdtTemplate = {
//
// NULL_SEL
//
{
0x0, // limit 15:0
0x0, // base 15:0
0x0, // base 23:16
0x0, // type
0x0, // limit 19:16, flags
0x0, // base 31:24
},
//
// LINEAR_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x092, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// LINEAR_CODE_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09A, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// SYS_DATA_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x092, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// SYS_CODE_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09A, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// LINEAR_CODE64_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09B, // present, ring 0, code, expand-up, writable
0x0AF, // LimitHigh (CS.L=1, CS.D=0)
0x0, // base (high)
},
//
// SPARE4_SEL
//
{
0x0, // limit 0
0x0, // base 0
0x0,
0x0, // present, ring 0, data, expand-up, writable
0x0, // page-granular, 32-bit
0x0,
},
//
// SPARE5_SEL
//
{
0x0, // limit 0
0x0, // base 0
0x0,
0x0, // present, ring 0, data, expand-up, writable
0x0, // page-granular, 32-bit
0x0,
},
};
/**
Initialize Global Descriptor Table.
**/
VOID
InitGlobalDescriptorTable (
VOID
)
{
GDT_ENTRIES *gdt;
IA32_DESCRIPTOR gdtPtr;
//
// Allocate Runtime Data for the GDT
//
gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
ASSERT (gdt != NULL);
gdt = ALIGN_POINTER (gdt, 8);
//
// Initialize all GDT entries
//
CopyMem(gdt, &GdtTemplate, sizeof (GdtTemplate));
//
// Write GDT register
//
//gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
gdtPtr.Base = (UINTN)(VOID*) gdt;
gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
AsmWriteGdtr (&gdtPtr);
//
// Update selector (segment) registers base on new GDT
//
SetCodeSelector ((UINT16)CPU_CODE_SEL);
SetDataSelectors ((UINT16)CPU_DATA_SEL);
}

365
CloverEFI/UefiCpuPkg/CpuDxe/Ia32/CpuAsm.S
View File

@ -1,365 +0,0 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#* CpuAsm.S
#*
#* Abstract:
#*
#------------------------------------------------------------------------------
#.MMX
#.XMM
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
#
# point to the external interrupt vector table
#
ExternalVectorTablePtr:
.byte 0, 0, 0, 0
ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
ASM_PFX(InitializeExternalVectorTablePtr):
movl 4(%esp), %eax
movl %eax, ExternalVectorTablePtr
ret
#------------------------------------------------------------------------------
# VOID
# SetCodeSelector (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SetCodeSelector)
ASM_PFX(SetCodeSelector):
movl 4(%esp), %ecx
subl $0x10, %esp
leal setCodeSelectorLongJump, %eax
movl %eax, (%esp)
movw %cx, 4(%esp)
.byte 0xFF, 0x2C, 0x24 # jmp *(%esp) note:(FWORD jmp)
setCodeSelectorLongJump:
addl $0x10, %esp
ret
#------------------------------------------------------------------------------
# VOID
# SetDataSelectors (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SetDataSelectors)
ASM_PFX(SetDataSelectors):
movl 4(%esp), %ecx
movw %cx, %ss
movw %cx, %ds
movw %cx, %es
movw %cx, %fs
movw %cx, %gs
ret
#---------------------------------------;
# CommonInterruptEntry ;
#---------------------------------------;
# The follow algorithm is used for the common interrupt routine.
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_PFX(CommonInterruptEntry):
cli
#
# All interrupt handlers are invoked through interrupt gates, so
# IF flag automatically cleared at the entry point
#
#
# Calculate vector number
#
# Get the return address of call, actually, it is the
# address of vector number.
#
xchgl (%esp), %ecx
movw (%ecx), %cx
andl $0x0FFFF, %ecx
cmpl $32, %ecx # Intel reserved vector for exceptions?
jae NoErrorCode
bt %ecx, ASM_PFX(mErrorCodeFlag)
jc HasErrorCode
NoErrorCode:
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + ECX +
# +---------------------+ <-- ESP
#
# Registers:
# ECX - Vector Number
#
#
# Put Vector Number on stack
#
pushl %ecx
#
# Put 0 (dummy) error code on stack, and restore ECX
#
xorl %ecx, %ecx # ECX = 0
xchgl 4(%esp), %ecx
jmp ErrorCodeAndVectorOnStack
HasErrorCode:
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + ECX +
# +---------------------+ <-- ESP
#
# Registers:
# ECX - Vector Number
#
#
# Put Vector Number on stack and restore ECX
#
xchgl (%esp), %ecx
ErrorCodeAndVectorOnStack:
pushl %ebp
movl %esp, %ebp
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + Vector Number +
# +---------------------+
# + EBP +
# +---------------------+ <-- EBP
#
#
# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
# is 16-byte aligned
#
andl $0x0fffffff0, %esp
subl $12, %esp
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
pushl %eax
pushl %ecx
pushl %edx
pushl %ebx
leal 24(%ebp), %ecx
pushl %ecx # ESP
pushl (%ebp) # EBP
pushl %esi
pushl %edi
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
movl %ss, %eax
pushl %eax
movzwl 16(%ebp), %eax
pushl %eax
movl %ds, %eax
pushl %eax
movl %es, %eax
pushl %eax
movl %fs, %eax
pushl %eax
movl %gs, %eax
pushl %eax
#; UINT32 Eip;
movl 12(%ebp), %eax
pushl %eax
#; UINT32 Gdtr[2], Idtr[2];
subl $8, %esp
sidt (%esp)
movl 2(%esp), %eax
xchgl (%esp), %eax
andl $0x0FFFF, %eax
movl %eax, 4(%esp)
subl $8, %esp
sgdt (%esp)
movl 2(%esp), %eax
xchgl (%esp), %eax
andl $0x0FFFF, %eax
movl %eax, 4(%esp)
#; UINT32 Ldtr, Tr;
xorl %eax, %eax
str %ax
pushl %eax
sldt %ax
pushl %eax
#; UINT32 EFlags;
movl 20(%ebp), %eax
pushl %eax
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
movl %cr4, %eax
orl $0x208, %eax
movl %eax, %cr4
pushl %eax
movl %cr3, %eax
pushl %eax
movl %cr2, %eax
pushl %eax
xorl %eax, %eax
pushl %eax
movl %cr0, %eax
pushl %eax
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
movl %dr7, %eax
pushl %eax
movl %dr6, %eax
pushl %eax
movl %dr3, %eax
pushl %eax
movl %dr2, %eax
pushl %eax
movl %dr1, %eax
pushl %eax
movl %dr0, %eax
pushl %eax
#; FX_SAVE_STATE_IA32 FxSaveState;
subl $512, %esp
movl %esp, %edi
.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld
#; UINT32 ExceptionData;
pushl 8(%ebp)
#; call into exception handler
movl ExternalVectorTablePtr, %eax # get the interrupt vectors base
orl %eax, %eax # NULL?
jz nullExternalExceptionHandler
mov 4(%ebp), %ecx
movl (%eax,%ecx,4), %eax
orl %eax, %eax # NULL?
jz nullExternalExceptionHandler
#; Prepare parameter and call
movl %esp, %edx
pushl %edx
movl 4(%ebp), %edx
pushl %edx
#
# Call External Exception Handler
#
call *%eax
addl $8, %esp
nullExternalExceptionHandler:
cli
#; UINT32 ExceptionData;
addl $4, %esp
#; FX_SAVE_STATE_IA32 FxSaveState;
movl %esp, %esi
.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
addl $512, %esp
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
#; Skip restoration of DRx registers to support in-circuit emualators
#; or debuggers set breakpoint in interrupt/exception context
addl $24, %esp
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
popl %eax
movl %eax, %cr0
addl $4, %esp # not for Cr1
popl %eax
movl %eax, %cr2
popl %eax
movl %eax, %cr3
popl %eax
movl %eax, %cr4
#; UINT32 EFlags;
popl 20(%ebp)
#; UINT32 Ldtr, Tr;
#; UINT32 Gdtr[2], Idtr[2];
#; Best not let anyone mess with these particular registers...
addl $24, %esp
#; UINT32 Eip;
popl 12(%ebp)
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
#; NOTE - modified segment registers could hang the debugger... We
#; could attempt to insulate ourselves against this possibility,
#; but that poses risks as well.
#;
popl %gs
popl %fs
popl %es
popl %ds
popl 16(%ebp)
popl %ss
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
popl %edi
popl %esi
addl $4, %esp # not for ebp
addl $4, %esp # not for esp
popl %ebx
popl %edx
popl %ecx
popl %eax
movl %ebp, %esp
popl %ebp
addl $8, %esp
iretl
#END

363
CloverEFI/UefiCpuPkg/CpuDxe/Ia32/CpuAsm.asm
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@ -1,363 +0,0 @@
TITLE CpuAsm.asm:
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
;* This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* CpuAsm.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
.686
.model flat,C
.code
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
;
; point to the external interrupt vector table
;
ExternalVectorTablePtr DWORD 0
InitializeExternalVectorTablePtr PROC PUBLIC
mov eax, [esp+4]
mov ExternalVectorTablePtr, eax
ret
InitializeExternalVectorTablePtr ENDP
;------------------------------------------------------------------------------
; VOID
; SetCodeSelector (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetCodeSelector PROC PUBLIC
mov ecx, [esp+4]
sub esp, 0x10
lea eax, setCodeSelectorLongJump
mov [esp], eax
mov [esp+4], cx
jmp fword ptr [esp]
setCodeSelectorLongJump:
add esp, 0x10
ret
SetCodeSelector ENDP
;------------------------------------------------------------------------------
; VOID
; SetDataSelectors (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetDataSelectors PROC PUBLIC
mov ecx, [esp+4]
mov ss, cx
mov ds, cx
mov es, cx
mov fs, cx
mov gs, cx
ret
SetDataSelectors ENDP
;---------------------------------------;
; CommonInterruptEntry ;
;---------------------------------------;
; The follow algorithm is used for the common interrupt routine.
CommonInterruptEntry PROC PUBLIC
cli
;
; All interrupt handlers are invoked through interrupt gates, so
; IF flag automatically cleared at the entry point
;
;
; Calculate vector number
;
; Get the return address of call, actually, it is the
; address of vector number.
;
xchg ecx, [esp]
mov cx, [ecx]
and ecx, 0FFFFh
cmp ecx, 32 ; Intel reserved vector for exceptions?
jae NoErrorCode
bt mErrorCodeFlag, ecx
jc HasErrorCode
NoErrorCode:
;
; Stack:
; +---------------------+
; + EFlags +
; +---------------------+
; + CS +
; +---------------------+
; + EIP +
; +---------------------+
; + ECX +
; +---------------------+ <-- ESP
;
; Registers:
; ECX - Vector Number
;
;
; Put Vector Number on stack
;
push ecx
;
; Put 0 (dummy) error code on stack, and restore ECX
;
xor ecx, ecx ; ECX = 0
xchg ecx, [esp+4]
jmp ErrorCodeAndVectorOnStack
HasErrorCode:
;
; Stack:
; +---------------------+
; + EFlags +
; +---------------------+
; + CS +
; +---------------------+
; + EIP +
; +---------------------+
; + Error Code +
; +---------------------+
; + ECX +
; +---------------------+ <-- ESP
;
; Registers:
; ECX - Vector Number
;
;
; Put Vector Number on stack and restore ECX
;
xchg ecx, [esp]
ErrorCodeAndVectorOnStack:
push ebp
mov ebp, esp
;
; Stack:
; +---------------------+
; + EFlags +
; +---------------------+
; + CS +
; +---------------------+
; + EIP +
; +---------------------+
; + Error Code +
; +---------------------+
; + Vector Number +
; +---------------------+
; + EBP +
; +---------------------+ <-- EBP
;
;
; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
; is 16-byte aligned
;
and esp, 0fffffff0h
sub esp, 12
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
push eax
push ecx
push edx
push ebx
lea ecx, [ebp + 6 * 4]
push ecx ; ESP
push dword ptr [ebp] ; EBP
push esi
push edi
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
mov eax, ss
push eax
movzx eax, word ptr [ebp + 4 * 4]
push eax
mov eax, ds
push eax
mov eax, es
push eax
mov eax, fs
push eax
mov eax, gs
push eax
;; UINT32 Eip;
mov eax, [ebp + 3 * 4]
push eax
;; UINT32 Gdtr[2], Idtr[2];
sub esp, 8
sidt [esp]
mov eax, [esp + 2]
xchg eax, [esp]
and eax, 0FFFFh
mov [esp+4], eax
sub esp, 8
sgdt [esp]
mov eax, [esp + 2]
xchg eax, [esp]
and eax, 0FFFFh
mov [esp+4], eax
;; UINT32 Ldtr, Tr;
xor eax, eax
str ax
push eax
sldt ax
push eax
;; UINT32 EFlags;
mov eax, [ebp + 5 * 4]
push eax
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
mov eax, cr4
or eax, 208h
mov cr4, eax
push eax
mov eax, cr3
push eax
mov eax, cr2
push eax
xor eax, eax
push eax
mov eax, cr0
push eax
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov eax, dr7
push eax
mov eax, dr6
push eax
mov eax, dr3
push eax
mov eax, dr2
push eax
mov eax, dr1
push eax
mov eax, dr0
push eax
;; FX_SAVE_STATE_IA32 FxSaveState;
sub esp, 512
mov edi, esp
db 0fh, 0aeh, 07h ;fxsave [edi]
;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld
;; UINT32 ExceptionData;
push dword ptr [ebp + 2 * 4]
;; call into exception handler
mov eax, ExternalVectorTablePtr ; get the interrupt vectors base
or eax, eax ; NULL?
jz nullExternalExceptionHandler
mov ecx, [ebp + 4]
mov eax, [eax + ecx * 4]
or eax, eax ; NULL?
jz nullExternalExceptionHandler
;; Prepare parameter and call
mov edx, esp
push edx
mov edx, dword ptr [ebp + 1 * 4]
push edx
;
; Call External Exception Handler
;
call eax
add esp, 8
nullExternalExceptionHandler:
cli
;; UINT32 ExceptionData;
add esp, 4
;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
db 0fh, 0aeh, 0eh ; fxrstor [esi]
add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
;; Skip restoration of DRx registers to support in-circuit emualators
;; or debuggers set breakpoint in interrupt/exception context
add esp, 4 * 6
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
pop eax
mov cr0, eax
add esp, 4 ; not for Cr1
pop eax
mov cr2, eax
pop eax
mov cr3, eax
pop eax
mov cr4, eax
;; UINT32 EFlags;
pop dword ptr [ebp + 5 * 4]
;; UINT32 Ldtr, Tr;
;; UINT32 Gdtr[2], Idtr[2];
;; Best not let anyone mess with these particular registers...
add esp, 24
;; UINT32 Eip;
pop dword ptr [ebp + 3 * 4]
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
;; NOTE - modified segment registers could hang the debugger... We
;; could attempt to insulate ourselves against this possibility,
;; but that poses risks as well.
;;
pop gs
pop fs
pop es
pop ds
pop dword ptr [ebp + 4 * 4]
pop ss
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
pop edi
pop esi
add esp, 4 ; not for ebp
add esp, 4 ; not for esp
pop ebx
pop edx
pop ecx
pop eax
mov esp, ebp
pop ebp
add esp, 8
iretd
CommonInterruptEntry ENDP
END

818
CloverEFI/UefiCpuPkg/CpuDxe/Ia32/IvtAsm.S
View File

@ -1,818 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# IvtAsm.S
#
# Abstract:
#
# Interrupt Vector Table
#
#------------------------------------------------------------------------------
#
# Interrupt Vector Table
#
ASM_GLOBAL ASM_PFX(AsmIdtVector00)
.p2align 3
ASM_PFX(AsmIdtVector00):
call ASM_PFX(CommonInterruptEntry)
.short 0x00
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x01
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x02
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x03
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x04
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x05
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x06
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x07
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x08
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x09
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x0a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x0b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x0c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x0d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x0e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x0f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x10
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x11
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x12
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x13
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x14
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x15
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x16
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x17
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x18
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x19
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x1a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x1b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x1c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x1d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x1e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x1f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x00
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x21
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x22
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x23
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x24
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x25
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x26
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x27
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x28
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x29
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x2a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x2b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x2c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x2d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x2e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x2f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x30
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x31
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x32
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x33
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x34
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x35
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x36
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x37
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x38
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x39
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x3a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x3b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x3c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x3d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x3e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x3f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x40
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x41
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x42
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x43
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x44
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x45
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x46
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x47
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x48
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x49
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x4a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x4b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x4c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x4d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x4e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x4f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x50
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x51
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x52
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x53
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x54
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x55
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x56
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x57
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x58
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x59
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x5a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x5b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x5c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x5d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x5e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x5f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x60
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x61
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x62
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x63
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x64
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x65
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x66
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x67
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x68
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x69
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x6a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x6b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x6c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x6d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x6e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x6f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x70
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x71
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x72
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x73
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x74
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x75
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x76
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x77
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x78
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x79
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x7a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x7b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x7c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x7d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x7e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x7f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x80
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x81
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x82
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x83
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x84
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x85
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x86
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x87
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x88
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x89
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x8a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x8b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x8c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x8d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x8e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x8f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x90
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x91
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x92
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x93
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x94
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x95
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x96
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x97
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x98
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x99
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x9a
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x9b
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x9c
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x9d
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x9e
nop
call ASM_PFX(CommonInterruptEntry)
.short 0x9f
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa0
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa1
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa2
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa3
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa4
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa5
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa6
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa7
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa8
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xa9
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xaa
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xab
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xac
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xad
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xae
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xaf
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb0
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb1
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb2
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb3
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb4
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb5
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb6
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb7
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb8
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xb9
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xba
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xbb
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xbc
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xbd
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xbe
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xbf
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc0
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc1
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc2
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc3
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc4
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc5
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc6
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc7
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc8
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xc9
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xca
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xcb
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xcc
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xcd
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xce
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xcf
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd0
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd1
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd2
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd3
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd4
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd5
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd6
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd7
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd8
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xd9
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xda
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xdb
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xdc
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xdd
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xde
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xdf
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe0
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe1
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe2
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe3
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe4
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe5
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe6
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe7
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe8
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xe9
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xea
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xeb
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xec
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xed
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xee
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xef
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf0
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf1
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf2
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf3
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf4
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf5
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf6
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf7
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf8
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xf9
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xfa
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xfb
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xfc
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xfd
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xfe
nop
call ASM_PFX(CommonInterruptEntry)
.short 0xff
nop
ASM_GLOBAL ASM_PFX(AsmCommonIdtEnd)
ASM_PFX(AsmCommonIdtEnd):
.byte 0

51
CloverEFI/UefiCpuPkg/CpuDxe/Ia32/IvtAsm.asm
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@ -1,51 +0,0 @@
TITLE IvtAsm.asm:
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>
;* This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* IvtAsm.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
#include <Base.h>
#ifdef MDE_CPU_IA32
.686
.model flat,C
#endif
.code
;------------------------------------------------------------------------------
; Generic IDT Vector Handlers for the Host. They are all the same so they
; will compress really well.
;
; By knowing the return address for Vector 00 you can can calculate the
; vector number by looking at the call CommonInterruptEntry return address.
; (return address - (AsmIdtVector00 + 5))/8 == IDT index
;
;------------------------------------------------------------------------------
EXTRN CommonInterruptEntry:PROC
ALIGN 8
PUBLIC AsmIdtVector00
AsmIdtVector00 LABEL BYTE
REPEAT 256
call CommonInterruptEntry
dw ($ - AsmIdtVector00 - 5) / 8 ; vector number
nop
ENDM
END

346
CloverEFI/UefiCpuPkg/CpuDxe/X64/CpuAsm.S
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@ -1,346 +0,0 @@
# TITLE CpuAsm.S:
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#* CpuAsm.S
#*
#* Abstract:
#*
#------------------------------------------------------------------------------
#text SEGMENT
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
#
# point to the external interrupt vector table
#
ExternalVectorTablePtr:
.byte 0, 0, 0, 0, 0, 0, 0, 0
ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
ASM_PFX(InitializeExternalVectorTablePtr):
leaq ExternalVectorTablePtr(%rip), %rax # save vector number
movq %rcx, (%rax)
ret
#------------------------------------------------------------------------------
# VOID
# SetCodeSelector (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SetCodeSelector)
ASM_PFX(SetCodeSelector):
subq $0x14, %rsp
leaq L_setCodeSelectorLongJump(%rip), %rax
movq %rax, (%rsp)
movw %cx, 4(%rsp)
.byte 0x48, 0xFF, 0x2C, 0x24 # jmp (%rsp) note:fword jmp
L_setCodeSelectorLongJump:
addq $0x14, %rsp
ret
#------------------------------------------------------------------------------
# VOID
# SetDataSelectors (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SetDataSelectors)
ASM_PFX(SetDataSelectors):
movw %cx, %ss
movw %cx, %ds
movw %cx, %es
movw %cx, %fs
movw %cx, %gs
ret
#---------------------------------------;
# CommonInterruptEntry ;
#---------------------------------------;
# The follow algorithm is used for the common interrupt routine.
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_PFX(CommonInterruptEntry):
cli
#
# All interrupt handlers are invoked through interrupt gates, so
# IF flag automatically cleared at the entry point
#
#
# Calculate vector number
#
xchgq (%rsp), %rcx # get the return address of call, actually, it is the address of vector number.
movzwl (%rcx), %ecx
cmp $32, %ecx # Intel reserved vector for exceptions?
jae NoErrorCode
pushq %rax
leaq ASM_PFX(mErrorCodeFlag)(%rip), %rax
bt %ecx, (%rax)
popq %rax
jc CommonInterruptEntry_al_0000
NoErrorCode:
#
# Push a dummy error code on the stack
# to maintain coherent stack map
#
pushq (%rsp)
movq $0, 8(%rsp)
CommonInterruptEntry_al_0000:
pushq %rbp
movq %rsp, %rbp
#
# Stack:
# +---------------------+ <-- 16-byte aligned ensured by processor
# + Old SS +
# +---------------------+
# + Old RSP +
# +---------------------+
# + RFlags +
# +---------------------+
# + CS +
# +---------------------+
# + RIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + RCX / Vector Number +
# +---------------------+
# + RBP +
# +---------------------+ <-- RBP, 16-byte aligned
#
#
# Since here the stack pointer is 16-byte aligned, so
# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
# is 16-byte aligned
#
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %r11
pushq %r10
pushq %r9
pushq %r8
pushq %rax
pushq 8(%rbp) # RCX
pushq %rdx
pushq %rbx
pushq 48(%rbp) # RSP
pushq (%rbp) # RBP
pushq %rsi
pushq %rdi
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
movzwq 56(%rbp), %rax
pushq %rax # for ss
movzwq 32(%rbp), %rax
pushq %rax # for cs
movl %ds, %eax
pushq %rax
movl %es, %eax
pushq %rax
movl %fs, %eax
pushq %rax
movl %gs, %eax
pushq %rax
movq %rcx, 8(%rbp) # save vector number
#; UINT64 Rip;
pushq 24(%rbp)
#; UINT64 Gdtr[2], Idtr[2];
xorq %rax, %rax
pushq %rax
pushq %rax
sidt (%rsp)
xchgq 2(%rsp), %rax
xchgq (%rsp), %rax
xchgq 8(%rsp), %rax
xorq %rax, %rax
pushq %rax
pushq %rax
sgdt (%rsp)
xchgq 2(%rsp), %rax
xchgq (%rsp), %rax
xchgq 8(%rsp), %rax
#; UINT64 Ldtr, Tr;
xorq %rax, %rax
str %ax
pushq %rax
sldt %ax
pushq %rax
#; UINT64 RFlags;
pushq 40(%rbp)
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
movq %cr8, %rax
pushq %rax
movq %cr4, %rax
orq $0x208, %rax
movq %rax, %cr4
pushq %rax
mov %cr3, %rax
pushq %rax
mov %cr2, %rax
pushq %rax
xorq %rax, %rax
pushq %rax
mov %cr0, %rax
pushq %rax
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
movq %dr7, %rax
pushq %rax
movq %dr6, %rax
pushq %rax
movq %dr3, %rax
pushq %rax
movq %dr2, %rax
pushq %rax
movq %dr1, %rax
pushq %rax
movq %dr0, %rax
pushq %rax
#; FX_SAVE_STATE_X64 FxSaveState;
subq $512, %rsp
movq %rsp, %rdi
.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
#; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld
#; UINT32 ExceptionData;
pushq 16(%rbp)
#; call into exception handler
movq 8(%rbp), %rcx
leaq ExternalVectorTablePtr(%rip), %rax
# movl (%eax), %eax
movq (%rax), %rax
movq (%rax,%rcx,8), %rax
orq %rax, %rax # NULL?
je nonNullValue#
#; Prepare parameter and call
# mov rcx, [rbp + 8]
mov %rsp, %rdx
#
# Per X64 calling convention, allocate maximum parameter stack space
# and make sure RSP is 16-byte aligned
#
subq $40, %rsp
call *%rax
addq $40, %rsp
nonNullValue:
cli
#; UINT64 ExceptionData;
addq $8, %rsp
#; FX_SAVE_STATE_X64 FxSaveState;
movq %rsp, %rsi
.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
addq $512, %rsp
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
#; Skip restoration of DRx registers to support in-circuit emualators
#; or debuggers set breakpoint in interrupt/exception context
addq $48, %rsp
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
popq %rax
movq %rax, %cr0
addq $8, %rsp # not for Cr1
popq %rax
movq %rax, %cr2
popq %rax
movq %rax, %cr3
popq %rax
movq %rax, %cr4
popq %rax
movq %rax, %cr8
#; UINT64 RFlags;
popq 40(%rbp)
#; UINT64 Ldtr, Tr;
#; UINT64 Gdtr[2], Idtr[2];
#; Best not let anyone mess with these particular registers...
addq $48, %rsp
#; UINT64 Rip;
popq 24(%rbp)
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
popq %rax
# mov %rax, %gs ; not for gs
popq %rax
# mov %rax, %fs ; not for fs
# (X64 will not use fs and gs, so we do not restore it)
popq %rax
movl %eax, %es
popq %rax
movl %eax, %ds
popq 32(%rbp) # for cs
popq 56(%rbp) # for ss
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
popq %rdi
popq %rsi
addq $8, %rsp # not for rbp
popq 48(%rbp) # for rsp
popq %rbx
popq %rdx
popq %rcx
popq %rax
popq %r8
popq %r9
popq %r10
popq %r11
popq %r12
popq %r13
popq %r14
popq %r15
movq %rbp, %rsp
popq %rbp
addq $16, %rsp
iretq
#text ENDS
#END

337
CloverEFI/UefiCpuPkg/CpuDxe/X64/CpuAsm.asm
View File

@ -1,337 +0,0 @@
TITLE CpuAsm.asm:
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
;* This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* CpuAsm.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
.code
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
;
; point to the external interrupt vector table
;
ExternalVectorTablePtr QWORD 0
InitializeExternalVectorTablePtr PROC PUBLIC
mov ExternalVectorTablePtr, rcx
ret
InitializeExternalVectorTablePtr ENDP
;------------------------------------------------------------------------------
; VOID
; SetCodeSelector (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetCodeSelector PROC PUBLIC
sub rsp, 0x14
lea rax, setCodeSelectorLongJump
mov [rsp], rax
mov [rsp+8], cx
;* I'm not sure how to encode this. We need to jmp [esp], where in esp there is
;* w16(selector):q64(address).
;* in gcc version this is encoded as 48 ff 2c 24 [ rex.W ljmpq (%esp) ]
;* but in VC jmp qword ptr [rsp] generates code ff 24 24 [ jmpq(%esp) ]
;* so I've just inserted db 0x48 to emit REX.W and get original 48 ff 2c 24
db 0x48
jmp fword ptr [rsp]
setCodeSelectorLongJump:
add rsp, 0x14
ret
SetCodeSelector ENDP
;------------------------------------------------------------------------------
; VOID
; SetDataSelectors (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetDataSelectors PROC PUBLIC
mov ss, cx
mov ds, cx
mov es, cx
mov fs, cx
mov gs, cx
ret
SetDataSelectors ENDP
;---------------------------------------;
; CommonInterruptEntry ;
;---------------------------------------;
; The follow algorithm is used for the common interrupt routine.
CommonInterruptEntry PROC PUBLIC
cli
;
; All interrupt handlers are invoked through interrupt gates, so
; IF flag automatically cleared at the entry point
;
;
; Calculate vector number
;
xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
movzx ecx, word ptr [rcx]
cmp ecx, 32 ; Intel reserved vector for exceptions?
jae NoErrorCode
bt mErrorCodeFlag, ecx
jc @F
NoErrorCode:
;
; Push a dummy error code on the stack
; to maintain coherent stack map
;
push [rsp]
mov qword ptr [rsp + 8], 0
@@:
push rbp
mov rbp, rsp
;
; Stack:
; +---------------------+ <-- 16-byte aligned ensured by processor
; + Old SS +
; +---------------------+
; + Old RSP +
; +---------------------+
; + RFlags +
; +---------------------+
; + CS +
; +---------------------+
; + RIP +
; +---------------------+
; + Error Code +
; +---------------------+
; + RCX / Vector Number +
; +---------------------+
; + RBP +
; +---------------------+ <-- RBP, 16-byte aligned
;
;
; Since here the stack pointer is 16-byte aligned, so
; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
; is 16-byte aligned
;
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rax
push qword ptr [rbp + 8] ; RCX
push rdx
push rbx
push qword ptr [rbp + 48] ; RSP
push qword ptr [rbp] ; RBP
push rsi
push rdi
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
movzx rax, word ptr [rbp + 56]
push rax ; for ss
movzx rax, word ptr [rbp + 32]
push rax ; for cs
mov rax, ds
push rax
mov rax, es
push rax
mov rax, fs
push rax
mov rax, gs
push rax
mov [rbp + 8], rcx ; save vector number
;; UINT64 Rip;
push qword ptr [rbp + 24]
;; UINT64 Gdtr[2], Idtr[2];
xor rax, rax
push rax
push rax
sidt [rsp]
xchg rax, [rsp + 2]
xchg rax, [rsp]
xchg rax, [rsp + 8]
xor rax, rax
push rax
push rax
sgdt [rsp]
xchg rax, [rsp + 2]
xchg rax, [rsp]
xchg rax, [rsp + 8]
;; UINT64 Ldtr, Tr;
xor rax, rax
str ax
push rax
sldt ax
push rax
;; UINT64 RFlags;
push qword ptr [rbp + 40]
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
mov rax, cr8
push rax
mov rax, cr4
or rax, 208h
mov cr4, rax
push rax
mov rax, cr3
push rax
mov rax, cr2
push rax
xor rax, rax
push rax
mov rax, cr0
push rax
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov rax, dr7
push rax
mov rax, dr6
push rax
mov rax, dr3
push rax
mov rax, dr2
push rax
mov rax, dr1
push rax
mov rax, dr0
push rax
;; FX_SAVE_STATE_X64 FxSaveState;
sub rsp, 512
mov rdi, rsp
db 0fh, 0aeh, 07h ;fxsave [rdi]
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld
;; UINT32 ExceptionData;
push qword ptr [rbp + 16]
;; call into exception handler
mov rcx, [rbp + 8]
mov rax, ExternalVectorTablePtr ; get the interrupt vectors base
mov rax, [rax + rcx * 8]
or rax, rax ; NULL?
je nonNullValue;
;; Prepare parameter and call
; mov rcx, [rbp + 8]
mov rdx, rsp
;
; Per X64 calling convention, allocate maximum parameter stack space
; and make sure RSP is 16-byte aligned
;
sub rsp, 4 * 8 + 8
call rax
add rsp, 4 * 8 + 8
nonNullValue:
cli
;; UINT64 ExceptionData;
add rsp, 8
;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp
db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
;; Skip restoration of DRx registers to support in-circuit emualators
;; or debuggers set breakpoint in interrupt/exception context
add rsp, 8 * 6
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
pop rax
mov cr0, rax
add rsp, 8 ; not for Cr1
pop rax
mov cr2, rax
pop rax
mov cr3, rax
pop rax
mov cr4, rax
pop rax
mov cr8, rax
;; UINT64 RFlags;
pop qword ptr [rbp + 40]
;; UINT64 Ldtr, Tr;
;; UINT64 Gdtr[2], Idtr[2];
;; Best not let anyone mess with these particular registers...
add rsp, 48
;; UINT64 Rip;
pop qword ptr [rbp + 24]
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
pop rax
; mov gs, rax ; not for gs
pop rax
; mov fs, rax ; not for fs
; (X64 will not use fs and gs, so we do not restore it)
pop rax
mov es, rax
pop rax
mov ds, rax
pop qword ptr [rbp + 32] ; for cs
pop qword ptr [rbp + 56] ; for ss
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
pop rdi
pop rsi
add rsp, 8 ; not for rbp
pop qword ptr [rbp + 48] ; for rsp
pop rbx
pop rdx
pop rcx
pop rax
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
mov rsp, rbp
pop rbp
add rsp, 16
iretq
CommonInterruptEntry ENDP
END

54
CloverEFI/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
View File

@ -1,54 +0,0 @@
## @file
# Produces the CPU I/O 2 Protocol.
#
# This DXE driver produces of the CPU I/O 2 Protocol, as introduced by PI 1.2.
#
# Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CpuIo2Dxe
FILE_GUID = A19B1FE7-C1BC-49F8-875F-54A5D542443F
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = CpuIo2Initialize
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
CpuIo2Dxe.c
CpuIo2Dxe.h
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
UefiDriverEntryPoint
BaseLib
DebugLib
IoLib
UefiBootServicesTableLib
[Protocols]
gEfiCpuIo2ProtocolGuid ## PRODUCES
[Depex]
TRUE
[BuildOptions]
XCODE:*_*_*_CC_FLAGS = -Os -DMDEPKG_NDEBUG
GCC:*_*_*_CC_FLAGS = -O0 -DMDEPKG_NDEBUG
MSFT:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG

48
CloverEFI/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
View File

@ -1,48 +0,0 @@
## @file
# Module that produces the SMM CPU I/O 2 Protocol using the services of the I/O Library
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CpuIo2Smm
FILE_GUID = A47EE2D8-F60E-42fd-8E58-7BD65EE4C29B
MODULE_TYPE = DXE_SMM_DRIVER
VERSION_STRING = 1.0
PI_SPECIFICATION_VERSION = 0x0001000A
ENTRY_POINT = SmmCpuIo2Initialize
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
CpuIo2Smm.c
CpuIo2Smm.h
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
UefiDriverEntryPoint
BaseLib
DebugLib
IoLib
SmmServicesTableLib
BaseMemoryLib
[Protocols]
gEfiSmmCpuIo2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[Depex]
TRUE

49
CloverEFI/UefiCpuPkg/CpuIoPei/CpuIoPei.inf
View File

@ -1,49 +0,0 @@
## @file
# Produces the CPU I/O PPI.
#
# This PEIM produces of the CPU I/O PPI.
#
# Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CpuIoPei
FILE_GUID = AE265864-CF5D-41a8-913D-71C155E76442
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = CpuIoInitialize
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources]
CpuIoPei.c
CpuIoPei.h
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
PeimEntryPoint
BaseLib
DebugLib
IoLib
PeiServicesLib
[Ppis]
gEfiPeiCpuIoPpiInstalledGuid # PPI ALWAYS_PRODUCED
[Depex]
TRUE

334
CloverEFI/UefiCpuPkg/Include/Library/MtrrLib.h
View File

@ -1,334 +0,0 @@
/** @file
MTRR setting library
Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MTRR_LIB_H_
#define _MTRR_LIB_H_
//
// According to IA32 SDM, MTRRs number and msr offset are always consistent
// for IA32 processor family
//
//
// The semantics of below macro is MAX_MTRR_NUMBER_OF_VARIABLE_MTRR, the real number can be read out from MTRR_CAP register.
//
#define MTRR_NUMBER_OF_VARIABLE_MTRR 32
//
// Firmware need reserve 2 MTRR for OS
//
#define RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER 2
#define MTRR_NUMBER_OF_FIXED_MTRR 11
//
// Below macro is deprecated, and should not be used.
//
#define FIRMWARE_VARIABLE_MTRR_NUMBER 6
#define MTRR_LIB_IA32_MTRR_CAP 0x0FE
#define MTRR_LIB_IA32_MTRR_CAP_VCNT_MASK 0x0FF
#define MTRR_LIB_IA32_MTRR_FIX64K_00000 0x250
#define MTRR_LIB_IA32_MTRR_FIX16K_80000 0x258
#define MTRR_LIB_IA32_MTRR_FIX16K_A0000 0x259
#define MTRR_LIB_IA32_MTRR_FIX4K_C0000 0x268
#define MTRR_LIB_IA32_MTRR_FIX4K_C8000 0x269
#define MTRR_LIB_IA32_MTRR_FIX4K_D0000 0x26A
#define MTRR_LIB_IA32_MTRR_FIX4K_D8000 0x26B
#define MTRR_LIB_IA32_MTRR_FIX4K_E0000 0x26C
#define MTRR_LIB_IA32_MTRR_FIX4K_E8000 0x26D
#define MTRR_LIB_IA32_MTRR_FIX4K_F0000 0x26E
#define MTRR_LIB_IA32_MTRR_FIX4K_F8000 0x26F
#define MTRR_LIB_IA32_VARIABLE_MTRR_BASE 0x200
//
// Below macro is deprecated, and should not be used.
//
#define MTRR_LIB_IA32_VARIABLE_MTRR_END 0x20F
#define MTRR_LIB_IA32_MTRR_DEF_TYPE 0x2FF
#define MTRR_LIB_MSR_VALID_MASK 0xFFFFFFFFFULL
#define MTRR_LIB_CACHE_VALID_ADDRESS 0xFFFFFF000ULL
#define MTRR_LIB_CACHE_MTRR_ENABLED 0x800
#define MTRR_LIB_CACHE_FIXED_MTRR_ENABLED 0x400
//
// Structure to describe a fixed MTRR
//
typedef struct {
UINT32 Msr;
UINT32 BaseAddress;
UINT32 Length;
} FIXED_MTRR;
//
// Structure to describe a variable MTRR
//
typedef struct {
UINT64 BaseAddress;
UINT64 Length;
UINT64 Type;
UINT32 Msr;
BOOLEAN Valid;
BOOLEAN Used;
} VARIABLE_MTRR;
//
// Structure to hold base and mask pair for variable MTRR register
//
typedef struct _MTRR_VARIABLE_SETTING_ {
UINT64 Base;
UINT64 Mask;
} MTRR_VARIABLE_SETTING;
//
// Array for variable MTRRs
//
typedef struct _MTRR_VARIABLE_SETTINGS_ {
MTRR_VARIABLE_SETTING Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
} MTRR_VARIABLE_SETTINGS;
//
// Array for fixed mtrrs
//
typedef struct _MTRR_FIXED_SETTINGS_ {
UINT64 Mtrr[MTRR_NUMBER_OF_FIXED_MTRR];
} MTRR_FIXED_SETTINGS;
//
// Structure to hold all MTRRs
//
typedef struct _MTRR_SETTINGS_ {
MTRR_FIXED_SETTINGS Fixed;
MTRR_VARIABLE_SETTINGS Variables;
UINT64 MtrrDefType;
} MTRR_SETTINGS;
//
// Memory cache types
//
typedef enum {
CacheUncacheable = 0,
CacheWriteCombining = 1,
CacheWriteThrough = 4,
CacheWriteProtected = 5,
CacheWriteBack = 6
} MTRR_MEMORY_CACHE_TYPE;
#define MTRR_CACHE_UNCACHEABLE 0
#define MTRR_CACHE_WRITE_COMBINING 1
#define MTRR_CACHE_WRITE_THROUGH 4
#define MTRR_CACHE_WRITE_PROTECTED 5
#define MTRR_CACHE_WRITE_BACK 6
#define MTRR_CACHE_INVALID_TYPE 7
/**
Returns the variable MTRR count for the CPU.
@return Variable MTRR count
**/
UINT32
EFIAPI
GetVariableMtrrCount (
VOID
);
/**
Returns the firmware usable variable MTRR count for the CPU.
@return Firmware usable variable MTRR count
**/
UINT32
EFIAPI
GetFirmwareVariableMtrrCount (
VOID
);
/**
This function attempts to set the attributes for a memory range.
@param BaseAddress The physical address that is the start address of a memory region.
@param Length The size in bytes of the memory region.
@param Attributes The bit mask of attributes to set for the memory region.
@retval RETURN_SUCCESS The attributes were set for the memory region.
@retval RETURN_INVALID_PARAMETER Length is zero.
@retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the
memory resource range specified by BaseAddress and Length.
@retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource
range specified by BaseAddress and Length.
@retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by
BaseAddress and Length cannot be modified.
@retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
the memory resource range.
**/
RETURN_STATUS
EFIAPI
MtrrSetMemoryAttribute (
IN PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN MTRR_MEMORY_CACHE_TYPE Attribute
);
/**
This function will get the memory cache type of the specific address.
This function is mainly for debugging purposes.
@param Address The specific address
@return The memory cache type of the specific address
**/
MTRR_MEMORY_CACHE_TYPE
EFIAPI
MtrrGetMemoryAttribute (
IN PHYSICAL_ADDRESS Address
);
/**
This function will get the raw value in variable MTRRs
@param VariableSettings A buffer to hold variable MTRRs content.
@return The buffer point to MTRR_VARIABLE_SETTINGS in which holds the content of the variable mtrr
**/
MTRR_VARIABLE_SETTINGS*
EFIAPI
MtrrGetVariableMtrr (
OUT MTRR_VARIABLE_SETTINGS *VariableSettings
);
/**
This function sets fixed MTRRs
@param VariableSettings A buffer to hold variable MTRRs content.
@return The pointer of VariableSettings
**/
MTRR_VARIABLE_SETTINGS*
EFIAPI
MtrrSetVariableMtrr (
IN MTRR_VARIABLE_SETTINGS *VariableSettings
);
/**
This function gets the content in fixed MTRRs
@param FixedSettings A buffer to hold fixed MTRRs content.
@return The pointer of FixedSettings
**/
MTRR_FIXED_SETTINGS*
EFIAPI
MtrrGetFixedMtrr (
OUT MTRR_FIXED_SETTINGS *FixedSettings
);
/**
This function sets fixed MTRRs
@param FixedSettings A buffer holding fixed MTRRs content.
@return The pointer of FixedSettings
**/
MTRR_FIXED_SETTINGS*
EFIAPI
MtrrSetFixedMtrr (
IN MTRR_FIXED_SETTINGS *FixedSettings
);
/**
This function gets the content in all MTRRs (variable and fixed)
@param MtrrSetting A buffer to hold all MTRRs content.
@return The pointer of MtrrSetting
**/
MTRR_SETTINGS *
EFIAPI
MtrrGetAllMtrrs (
OUT MTRR_SETTINGS *MtrrSetting
);
/**
This function sets all MTRRs (variable and fixed)
@param MtrrSetting A buffer to hold all MTRRs content.
@return The pointer of MtrrSetting
**/
MTRR_SETTINGS *
EFIAPI
MtrrSetAllMtrrs (
IN MTRR_SETTINGS *MtrrSetting
);
/**
Get the attribute of variable MTRRs.
This function shadows the content of variable MTRRs into
an internal array: VariableMtrr
@param MtrrValidBitsMask The mask for the valid bit of the MTRR
@param MtrrValidAddressMask The valid address mask for MTRR since the base address in
MTRR must align to 4K, so valid address mask equal to
MtrrValidBitsMask & 0xfffffffffffff000ULL
@param VariableMtrr The array to shadow variable MTRRs content
@return The ruturn value of this paramter indicates the number of
MTRRs which has been used.
**/
UINT32
EFIAPI
MtrrGetMemoryAttributeInVariableMtrr (
IN UINT64 MtrrValidBitsMask,
IN UINT64 MtrrValidAddressMask,
OUT VARIABLE_MTRR *VariableMtrr
);
/**
This function prints all MTRRs for debugging.
**/
VOID
EFIAPI
MtrrDebugPrintAllMtrrs (
VOID
);
/**
Checks if MTRR is supported.
@retval TRUE MTRR is supported.
@retval FALSE MTRR is not supported.
**/
BOOLEAN
EFIAPI
IsMtrrSupported (
VOID
);
#endif // _MTRR_LIB_H_

743
CloverEFI/UefiCpuPkg/Include/Register/Amd/Cpuid.h
View File

@ -1,743 +0,0 @@
/** @file
CPUID leaf definitions.
Provides defines for CPUID leaf indexes. Data structures are provided for
registers returned by a CPUID leaf that contain one or more bit fields.
If a register returned is a single 32-bit value, then a data structure is
not provided for that register.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
**/
#ifndef __AMD_CPUID_H__
#define __AMD_CPUID_H__
/**
CPUID Signature Information
@param EAX CPUID_SIGNATURE (0x00)
@retval EAX Returns the highest value the CPUID instruction recognizes for
returning basic processor information. The value is returned is
processor specific.
@retval EBX First 4 characters of a vendor identification string.
@retval ECX Last 4 characters of a vendor identification string.
@retval EDX Middle 4 characters of a vendor identification string.
**/
///
/// @{ CPUID signature values returned by AMD processors
///
#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')
#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')
#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')
///
/// @}
///
/**
CPUID Extended Processor Signature and Features
@param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
@retval EAX Extended Family, Model, Stepping Identifiers
described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
@retval EBX Brand Identifier
described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
@retval ECX Extended Feature Identifiers
described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
@retval EDX Extended Feature Identifiers
described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
**/
/**
CPUID Extended Processor Signature and Features EAX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 3:0] Stepping.
///
UINT32 Stepping:4;
///
/// [Bits 7:4] Base Model.
///
UINT32 BaseModel:4;
///
/// [Bits 11:8] Base Family.
///
UINT32 BaseFamily:4;
///
/// [Bit 15:12] Reserved.
///
UINT32 Reserved1:4;
///
/// [Bits 19:16] Extended Model.
///
UINT32 ExtModel:4;
///
/// [Bits 27:20] Extended Family.
///
UINT32 ExtFamily:8;
///
/// [Bit 31:28] Reserved.
///
UINT32 Reserved2:4;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
/**
CPUID Extended Processor Signature and Features EBX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 27:0] Reserved.
///
UINT32 Reserved:28;
///
/// [Bit 31:28] Package Type.
///
UINT32 PkgType:4;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
/**
CPUID Extended Processor Signature and Features ECX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] LAHF/SAHF available in 64-bit mode.
///
UINT32 LAHF_SAHF:1;
///
/// [Bit 1] Core multi-processing legacy mode.
///
UINT32 CmpLegacy:1;
///
/// [Bit 2] Secure Virtual Mode feature.
///
UINT32 SVM:1;
///
/// [Bit 3] Extended APIC register space.
///
UINT32 ExtApicSpace:1;
///
/// [Bit 4] LOCK MOV CR0 means MOV CR8.
///
UINT32 AltMovCr8:1;
///
/// [Bit 5] LZCNT instruction support.
///
UINT32 LZCNT:1;
///
/// [Bit 6] SSE4A instruction support.
///
UINT32 SSE4A:1;
///
/// [Bit 7] Misaligned SSE Mode.
///
UINT32 MisAlignSse:1;
///
/// [Bit 8] ThreeDNow Prefetch instructions.
///
UINT32 PREFETCHW:1;
///
/// [Bit 9] OS Visible Work-around support.
///
UINT32 OSVW:1;
///
/// [Bit 10] Instruction Based Sampling.
///
UINT32 IBS:1;
///
/// [Bit 11] Extended Operation Support.
///
UINT32 XOP:1;
///
/// [Bit 12] SKINIT and STGI support.
///
UINT32 SKINIT:1;
///
/// [Bit 13] Watchdog Timer support.
///
UINT32 WDT:1;
///
/// [Bit 14] Reserved.
///
UINT32 Reserved1:1;
///
/// [Bit 15] Lightweight Profiling support.
///
UINT32 LWP:1;
///
/// [Bit 16] 4-Operand FMA instruction support.
///
UINT32 FMA4:1;
///
/// [Bit 17] Translation Cache Extension.
///
UINT32 TCE:1;
///
/// [Bit 21:18] Reserved.
///
UINT32 Reserved2:4;
///
/// [Bit 22] Topology Extensions support.
///
UINT32 TopologyExtensions:1;
///
/// [Bit 23] Core Performance Counter Extensions.
///
UINT32 PerfCtrExtCore:1;
///
/// [Bit 25:24] Reserved.
///
UINT32 Reserved3:2;
///
/// [Bit 26] Data Breakpoint Extension.
///
UINT32 DataBreakpointExtension:1;
///
/// [Bit 27] Performance Time-Stamp Counter.
///
UINT32 PerfTsc:1;
///
/// [Bit 28] L3 Performance Counter Extensions.
///
UINT32 PerfCtrExtL3:1;
///
/// [Bit 29] MWAITX and MONITORX capability.
///
UINT32 MwaitExtended:1;
///
/// [Bit 31:30] Reserved.
///
UINT32 Reserved4:2;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
/**
CPUID Extended Processor Signature and Features EDX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] x87 floating point unit on-chip.
///
UINT32 FPU:1;
///
/// [Bit 1] Virtual-mode enhancements.
///
UINT32 VME:1;
///
/// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
///
UINT32 DE:1;
///
/// [Bit 3] Page-size extensions (4 MB pages).
///
UINT32 PSE:1;
///
/// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
///
UINT32 TSC:1;
///
/// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
///
UINT32 MSR:1;
///
/// [Bit 6] Physical-address extensions (PAE).
///
UINT32 PAE:1;
///
/// [Bit 7] Machine check exception, CR4.MCE.
///
UINT32 MCE:1;
///
/// [Bit 8] CMPXCHG8B instruction.
///
UINT32 CMPXCHG8B:1;
///
/// [Bit 9] APIC exists and is enabled.
///
UINT32 APIC:1;
///
/// [Bit 10] Reserved.
///
UINT32 Reserved1:1;
///
/// [Bit 11] SYSCALL and SYSRET instructions.
///
UINT32 SYSCALL_SYSRET:1;
///
/// [Bit 12] Memory-type range registers.
///
UINT32 MTRR:1;
///
/// [Bit 13] Page global extension, CR4.PGE.
///
UINT32 PGE:1;
///
/// [Bit 14] Machine check architecture, MCG_CAP.
///
UINT32 MCA:1;
///
/// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
///
UINT32 CMOV:1;
///
/// [Bit 16] Page attribute table.
///
UINT32 PAT:1;
///
/// [Bit 17] Page-size extensions.
///
UINT32 PSE36 : 1;
///
/// [Bit 19:18] Reserved.
///
UINT32 Reserved2:2;
///
/// [Bit 20] No-execute page protection.
///
UINT32 NX:1;
///
/// [Bit 21] Reserved.
///
UINT32 Reserved3:1;
///
/// [Bit 22] AMD Extensions to MMX instructions.
///
UINT32 MmxExt:1;
///
/// [Bit 23] MMX instructions.
///
UINT32 MMX:1;
///
/// [Bit 24] FXSAVE and FXRSTOR instructions.
///
UINT32 FFSR:1;
///
/// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
///
UINT32 FFXSR:1;
///
/// [Bit 26] 1-GByte large page support.
///
UINT32 Page1GB:1;
///
/// [Bit 27] RDTSCP intructions.
///
UINT32 RDTSCP:1;
///
/// [Bit 28] Reserved.
///
UINT32 Reserved4:1;
///
/// [Bit 29] Long Mode.
///
UINT32 LM:1;
///
/// [Bit 30] 3DNow! instructions.
///
UINT32 ThreeDNow:1;
///
/// [Bit 31] AMD Extensions to 3DNow! instructions.
///
UINT32 ThreeDNowExt:1;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
/**
CPUID Linear Physical Address Size
@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
@retval EAX Linear/Physical Address Size described by the type
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
@retval EBX Linear/Physical Address Size described by the type
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
@retval ECX Linear/Physical Address Size described by the type
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
@retval EDX Reserved.
**/
/**
CPUID Linear Physical Address Size EAX for CPUID leaf
#CPUID_VIR_PHY_ADDRESS_SIZE.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Maximum physical byte address size in bits.
///
UINT32 PhysicalAddressBits:8;
///
/// [Bits 15:8] Maximum linear byte address size in bits.
///
UINT32 LinearAddressBits:8;
///
/// [Bits 23:16] Maximum guest physical byte address size in bits.
///
UINT32 GuestPhysAddrSize:8;
///
/// [Bit 31:24] Reserved.
///
UINT32 Reserved:8;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
/**
CPUID Linear Physical Address Size EBX for CPUID leaf
#CPUID_VIR_PHY_ADDRESS_SIZE.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 0] Clear Zero Instruction.
///
UINT32 CLZERO:1;
///
/// [Bits 1] Instructions retired count support.
///
UINT32 IRPerf:1;
///
/// [Bits 2] Restore error pointers for XSave instructions.
///
UINT32 XSaveErPtr:1;
///
/// [Bit 31:3] Reserved.
///
UINT32 Reserved:29;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
/**
CPUID Linear Physical Address Size ECX for CPUID leaf
#CPUID_VIR_PHY_ADDRESS_SIZE.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Number of threads - 1.
///
UINT32 NC:8;
///
/// [Bit 11:8] Reserved.
///
UINT32 Reserved1:4;
///
/// [Bits 15:12] APIC ID size.
///
UINT32 ApicIdCoreIdSize:4;
///
/// [Bits 17:16] Performance time-stamp counter size.
///
UINT32 PerfTscSize:2;
///
/// [Bit 31:18] Reserved.
///
UINT32 Reserved2:14;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
/**
CPUID AMD Processor Topology
@param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
@retval EAX Extended APIC ID described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
@retval EBX Core Indentifiers described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
@retval ECX Node Indentifiers described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
@retval EDX Reserved.
**/
#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
/**
CPUID AMD Processor Topology EAX for CPUID leaf
#CPUID_AMD_PROCESSOR_TOPOLOGY.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 31:0] Extended APIC Id.
///
UINT32 ExtendedApicId;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
/**
CPUID AMD Processor Topology EBX for CPUID leaf
#CPUID_AMD_PROCESSOR_TOPOLOGY.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Core Id.
///
UINT32 CoreId:8;
///
/// [Bits 15:8] Threads per core.
///
UINT32 ThreadsPerCore:8;
///
/// [Bit 31:16] Reserved.
///
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
/**
CPUID AMD Processor Topology ECX for CPUID leaf
#CPUID_AMD_PROCESSOR_TOPOLOGY.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Node Id.
///
UINT32 NodeId:8;
///
/// [Bits 10:8] Nodes per processor.
///
UINT32 NodesPerProcessor:3;
///
/// [Bit 31:11] Reserved.
///
UINT32 Reserved:21;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
/**
CPUID Memory Encryption Information
@param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
@retval EAX Returns the memory encryption feature support status.
@retval EBX If memory encryption feature is present then return
the page table bit number used to enable memory encryption support
and reducing of physical address space in bits.
@retval ECX Returns number of encrypted guest supported simultaneously.
@retval EDX Returns minimum SEV enabled and SEV disabled ASID.
<b>Example usage</b>
@code
UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
@endcode
**/
#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F
/**
CPUID Memory Encryption support information EAX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Secure Memory Encryption (Sme) Support
///
UINT32 SmeBit:1;
///
/// [Bit 1] Secure Encrypted Virtualization (Sev) Support
///
UINT32 SevBit:1;
///
/// [Bit 2] Page flush MSR support
///
UINT32 PageFlushMsrBit:1;
///
/// [Bit 3] Encrypted state support
///
UINT32 SevEsBit:1;
///
/// [Bit 31:4] Reserved
///
UINT32 ReservedBits:28;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_EAX;
/**
CPUID Memory Encryption support information EBX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 5:0] Page table bit number used to enable memory encryption
///
UINT32 PtePosBits:6;
///
/// [Bit 11:6] Reduction of system physical address space bits when
/// memory encryption is enabled
///
UINT32 ReducedPhysBits:5;
///
/// [Bit 31:12] Reserved
///
UINT32 ReservedBits:21;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_EBX;
/**
CPUID Memory Encryption support information ECX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 31:0] Number of encrypted guest supported simultaneously
///
UINT32 NumGuests;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_ECX;
/**
CPUID Memory Encryption support information EDX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
///
UINT32 MinAsid;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_EDX;
#endif

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CloverEFI/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h
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/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
**/
#ifndef __FAM17_MSR_H__
#define __FAM17_MSR_H__
/**
Secure Encrypted Virtualization (SEV) status register
**/
#define MSR_SEV_STATUS 0xc0010131
/**
MSR information returned for #MSR_SEV_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
///
UINT32 SevBit:1;
///
/// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
///
UINT32 SevEsBit:1;
UINT32 Reserved:30;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_SEV_STATUS_REGISTER;
#endif

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/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
**/
#ifndef __AMD_MSR_H__
#define __AMD_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Amd/Fam17Msr.h>
#endif

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CloverEFI/UefiCpuPkg/Include/Register/LocalApic.h
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/** @file
IA32 Local APIC Definitions.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __LOCAL_APIC_H__
#define __LOCAL_APIC_H__
//
// Definitions for IA32 architectural MSRs
//
#define MSR_IA32_APIC_BASE_ADDRESS 0x1B
//
// Definitions for CPUID instruction
//
#define CPUID_VERSION_INFO 0x1
#define CPUID_EXTENDED_FUNCTION 0x80000000
#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
//
// Definition for Local APIC registers and related values
//
#define XAPIC_ID_OFFSET 0x20
#define XAPIC_VERSION_OFFSET 0x30
#define XAPIC_EOI_OFFSET 0x0b0
#define XAPIC_ICR_DFR_OFFSET 0x0e0
#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
#define XAPIC_ICR_LOW_OFFSET 0x300
#define XAPIC_ICR_HIGH_OFFSET 0x310
#define XAPIC_LVT_TIMER_OFFSET 0x320
#define XAPIC_LVT_LINT0_OFFSET 0x350
#define XAPIC_LVT_LINT1_OFFSET 0x360
#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
#define X2APIC_MSR_BASE_ADDRESS 0x800
#define X2APIC_MSR_ICR_ADDRESS 0x830
#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
#define LOCAL_APIC_DELIVERY_MODE_SMI 2
#define LOCAL_APIC_DELIVERY_MODE_NMI 4
#define LOCAL_APIC_DELIVERY_MODE_INIT 5
#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
typedef union {
struct {
UINT32 Reserved0:8; ///< Reserved.
UINT32 Bsp:1; ///< Processor is BSP.
UINT32 Reserved1:1; ///< Reserved.
UINT32 Extd:1; ///< Enable x2APIC mode.
UINT32 En:1; ///< xAPIC global enable/disable.
UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
UINT32 ApicBaseHigh:32;
} Bits;
UINT64 Uint64;
} MSR_IA32_APIC_BASE;
//
// Local APIC Version Register.
//
typedef union {
struct {
UINT32 Version:8; ///< The version numbers of the local APIC.
UINT32 Reserved0:8; ///< Reserved.
UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.
UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.
UINT32 Reserved1:7; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_VERSION;
//
// Low half of Interrupt Command Register (ICR).
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
UINT32 Reserved0:1; ///< Reserved.
UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
UINT32 Reserved1:2; ///< Reserved.
UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
UINT32 Reserved2:12; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_ICR_LOW;
//
// High half of Interrupt Command Register (ICR)
//
typedef union {
struct {
UINT32 Reserved0:24; ///< Reserved.
UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
} Bits;
UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
} LOCAL_APIC_ICR_HIGH;
//
// Spurious-Interrupt Vector Register (SVR)
//
typedef union {
struct {
UINT32 SpuriousVector:8; ///< Spurious Vector.
UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
UINT32 Reserved0:2; ///< Reserved.
UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
UINT32 Reserved1:19; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_SVR;
//
// Divide Configuration Register (DCR)
//
typedef union {
struct {
UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
UINT32 Reserved0:1; ///< Always 0.
UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
UINT32 Reserved1:28; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_DCR;
//
// LVT Timer Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 Reserved0:4; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 Reserved1:3; ///< Reserved.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
UINT32 Reserved2:14; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_TIMER;
//
// LVT LINT0/LINT1 Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:1; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
UINT32 TriggerMode:1; ///< 0:edge, 1:level.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 Reserved1:15; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_LINT;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Reserved0:2; ///< Reserved
UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
UINT32 Reserved1:8; ///< Reserved.
UINT32 DestinationId:8; ///< Specifies the Destination ID.
UINT32 BaseAddress:12; ///< Must be 0FEEH
} Bits;
UINT32 Uint32;
} LOCAL_APIC_MSI_ADDRESS;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:3; ///< Reserved.
UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
UINT32 Reserved1:16; ///< Reserved.
UINT32 Reserved2:32; ///< Reserved.
} Bits;
UINT64 Uint64;
} LOCAL_APIC_MSI_DATA;
#endif

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CloverEFI/UefiCpuPkg/Include/Register/Microcode.h
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/** @file
Microcode Definitions.
Microcode Definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3A, Section 9.11 Microcode Definitions
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
**/
#ifndef __MICROCODE_H__
#define __MICROCODE_H__
///
/// CPU Microcode Date in BCD format
///
typedef union {
struct {
UINT32 Year:16;
UINT32 Day:8;
UINT32 Month:8;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_DATE;
///
/// CPU Microcode Processor Signature format
///
typedef union {
struct {
UINT32 Stepping:4;
UINT32 Model:4;
UINT32 Family:4;
UINT32 Type:2;
UINT32 Reserved1:2;
UINT32 ExtendedModel:4;
UINT32 ExtendedFamily:8;
UINT32 Reserved2:4;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_PROCESSOR_SIGNATURE;
#pragma pack (1)
///
/// Microcode Update Format definition
///
typedef struct {
///
/// Version number of the update header
///
UINT32 HeaderVersion;
///
/// Unique version number for the update, the basis for the update
/// signature provided by the processor to indicate the current update
/// functioning within the processor. Used by the BIOS to authenticate
/// the update and verify that the processor loads successfully. The
/// value in this field cannot be used for processor stepping identification
/// alone. This is a signed 32-bit number.
///
UINT32 UpdateRevision;
///
/// Date of the update creation in binary format: mmddyyyy (e.g.
/// 07/18/98 is 07181998H).
///
CPU_MICROCODE_DATE Date;
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Checksum of Update Data and Header. Used to verify the integrity of
/// the update header and data. Checksum is correct when the
/// summation of all the DWORDs (including the extended Processor
/// Signature Table) that comprise the microcode update result in
/// 00000000H.
///
UINT32 Checksum;
///
/// Version number of the loader program needed to correctly load this
/// update. The initial version is 00000001H
///
UINT32 LoaderRevision;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlags;
///
/// Specifies the size of the encrypted data in bytes, and must be a
/// multiple of DWORDs. If this value is 00000000H, then the microcode
/// update encrypted data is 2000 bytes (or 500 DWORDs).
///
UINT32 DataSize;
///
/// Specifies the total size of the microcode update in bytes. It is the
/// summation of the header size, the encrypted data size and the size of
/// the optional extended signature table. This value is always a multiple
/// of 1024.
///
UINT32 TotalSize;
///
/// Reserved fields for future expansion.
///
UINT8 Reserved[12];
} CPU_MICROCODE_HEADER;
///
/// Extended Signature Table Header Field Definitions
///
typedef struct {
///
/// Specifies the number of extended signature structures (Processor
/// Signature[n], processor flags[n] and checksum[n]) that exist in this
/// microcode update
///
UINT32 ExtendedSignatureCount;
///
/// Checksum of update extended processor signature table. Used to
/// verify the integrity of the extended processor signature table.
/// Checksum is correct when the summation of the DWORDs that
/// comprise the extended processor signature table results in
/// 00000000H.
///
UINT32 ExtendedChecksum;
///
/// Reserved fields.
///
UINT8 Reserved[12];
} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
///
/// Extended Signature Table Field Definitions
///
typedef struct {
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlag;
///
/// Used by utility software to decompose a microcode update into
/// multiple microcode updates where each of the new updates is
/// constructed without the optional Extended Processor Signature
/// Table.
/// To calculate the Checksum, substitute the Primary Processor
/// Signature entry and the Processor Flags entry with the
/// corresponding Extended Patch entry. Delete the Extended Processor
/// Signature Table entries. The Checksum is correct when the
/// summation of all DWORDs that comprise the created Extended
/// Processor Patch results in 00000000H.
///
UINT32 Checksum;
} CPU_MICROCODE_EXTENDED_TABLE;
#pragma pack ()
#endif

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/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
**/
#ifndef __MSR_H__
#define __MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Msr/Core2Msr.h>
#include <Register/Msr/AtomMsr.h>
#include <Register/Msr/SilvermontMsr.h>
#include <Register/Msr/GoldmontMsr.h>
#include <Register/Msr/NehalemMsr.h>
#include <Register/Msr/Xeon5600Msr.h>
#include <Register/Msr/XeonE7Msr.h>
#include <Register/Msr/SandyBridgeMsr.h>
#include <Register/Msr/IvyBridgeMsr.h>
#include <Register/Msr/HaswellMsr.h>
#include <Register/Msr/HaswellEMsr.h>
#include <Register/Msr/BroadwellMsr.h>
#include <Register/Msr/XeonDMsr.h>
#include <Register/Msr/SkylakeMsr.h>
#include <Register/Msr/XeonPhiMsr.h>
#include <Register/Msr/Pentium4Msr.h>
#include <Register/Msr/CoreMsr.h>
#include <Register/Msr/PentiumMMsr.h>
#include <Register/Msr/P6Msr.h>
#include <Register/Msr/PentiumMsr.h>
#endif

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@ -1,790 +0,0 @@
/** @file
MSR Definitions for the Intel(R) Atom(TM) Processor Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.
**/
#ifndef __ATOM_MSR_H__
#define __ATOM_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Atom(TM) Processor Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x1C || \
DisplayModel == 0x26 || \
DisplayModel == 0x27 || \
DisplayModel == 0x35 || \
DisplayModel == 0x36 \
) \
)
/**
Shared. Model Specific Platform ID (R).
@param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PLATFORM_ID_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
@endcode
@note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
**/
#define MSR_ATOM_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:8;
///
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
///
UINT32 MaximumQualifiedRatio:5;
UINT32 Reserved2:19;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PLATFORM_ID_REGISTER;
/**
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
processor features; (R) indicates current processor configuration.
@param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
@endcode
@note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 DataErrorCheckingEnable:1;
///
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 ResponseErrorCheckingEnable:1;
///
/// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
///
UINT32 AERR_DriveEnable:1;
///
/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
/// Disabled Always 0.
///
UINT32 BERR_Enable:1;
UINT32 Reserved2:1;
UINT32 Reserved3:1;
///
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
///
UINT32 BINIT_DriverEnable:1;
UINT32 Reserved4:1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 ExecuteBIST:1;
///
/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 AERR_ObservationEnabled:1;
UINT32 Reserved5:1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 BINIT_ObservationEnabled:1;
UINT32 Reserved6:1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
///
UINT32 ResetVector:1;
UINT32 Reserved7:1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
///
UINT32 APICClusterID:2;
UINT32 Reserved8:2;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
///
UINT32 SymmetricArbitrationID:2;
///
/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
///
UINT32 IntegerBusFrequencyRatio:5;
UINT32 Reserved9:5;
UINT32 Reserved10:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_EBL_CR_POWERON_REGISTER;
/**
Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The From_IP part of the
stack contains pointers to the source instruction . See also: - Last Branch
Record Stack TOS at 1C9H - Section 17.5.
@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
@{
**/
#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
/// @}
/**
Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The To_IP part of the
stack contains pointers to the destination instruction.
@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
@{
**/
#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
/// @}
/**
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
bus clock speed for processors based on Intel Atom microarchitecture:.
@param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_FSB_FREQ_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
@endcode
@note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
**/
#define MSR_ATOM_FSB_FREQ 0x000000CD
/**
MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 2:0] - Scalable Bus Speed
///
/// Atom Processor Family
/// ---------------------
/// 111B: 083 MHz (FSB 333)
/// 101B: 100 MHz (FSB 400)
/// 001B: 133 MHz (FSB 533)
/// 011B: 167 MHz (FSB 667)
///
/// 133.33 MHz should be utilized if performing calculation with
/// System Bus Speed when encoding is 001B.
/// 166.67 MHz should be utilized if performing calculation with
/// System Bus Speed when
/// encoding is 011B.
///
UINT32 ScalableBusSpeed:3;
UINT32 Reserved1:29;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_FSB_FREQ_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
@endcode
@note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
#define MSR_ATOM_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
UINT32 L2HardwareEnabled:1;
UINT32 Reserved1:7;
///
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
UINT32 L2Enabled:1;
UINT32 Reserved2:14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
UINT32 L2NotPresent:1;
UINT32 Reserved3:8;
UINT32 Reserved4:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_BBL_CR_CTL3_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_PERF_STATUS (0x00000198)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PERF_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
@endcode
@note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
**/
#define MSR_ATOM_PERF_STATUS 0x00000198
/**
MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 15:0] Current Performance State Value.
///
UINT32 CurrentPerformanceStateValue:16;
UINT32 Reserved1:16;
UINT32 Reserved2:8;
///
/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
/// configured for the processor.
///
UINT32 MaximumBusRatio:5;
UINT32 Reserved3:19;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PERF_STATUS_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_THERM2_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
@endcode
@note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
#define MSR_ATOM_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
///
UINT32 TM_SELECT:1;
UINT32 Reserved2:15;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_THERM2_CTL_REGISTER;
/**
Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
@note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Fast-Strings Enable See Table 35-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
UINT32 Reserved4:1;
///
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
/// the processor to indicate a pending break event within the processor 0
/// = Indicates compatible FERR# signaling behavior This bit must be set
/// to 1 to support XAPIC interrupt model usage.
///
UINT32 FERR:1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
///
UINT32 PEBS:1;
///
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
/// thermal sensor indicates that the die temperature is at the
/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
/// TM2 will reduce the bus to core ratio and voltage according to the
/// value last written to MSR_THERM2_CTL bits 15:0.
/// When this bit is clear (0, default), the processor does not change
/// the VID signals or the bus to core ratio when the processor enters a
/// thermally managed state. The BIOS must enable this feature if the
/// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
/// not set, this feature is not supported and BIOS must not alter the
/// contents of the TM2 bit location. The processor is operating out of
/// specification if both this bit and the TM1 bit are set to 0.
///
UINT32 TM2:1;
UINT32 Reserved5:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
///
UINT32 EIST:1;
UINT32 Reserved6:1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
///
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
/// (R/WO) When set, this bit causes the following bits to become
/// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
/// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
/// be set before an Enhanced Intel SpeedStep Technology transition is
/// requested. This bit is cleared on reset.
///
UINT32 EISTLock:1;
UINT32 Reserved8:1;
///
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved9:8;
UINT32 Reserved10:2;
///
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
/**
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
that points to the MSR containing the most recent branch record. See
MSR_LASTBRANCH_0_FROM_IP (at 40H).
@param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
/**
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
@param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
@endcode
@note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_ATOM_LER_FROM_LIP 0x000001DD
/**
Unique. Last Exception Record To Linear IP (R) This area contains a pointer
to the target of the last branch instruction that the processor executed
prior to the last exception that was generated or the last interrupt that
was handled.
@param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
@endcode
@note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_ATOM_LER_TO_LIP 0x000001DE
/**
Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
@endcode
@note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
#define MSR_ATOM_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
///
UINT32 Enable:1;
UINT32 Reserved1:31;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PEBS_ENABLE_REGISTER;
/**
Package. Package C2 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C2 Residency Counter. (R/O) Time that this
package is in processor-specific C2 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
/**
Package. Package C4 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C4 Residency Counter. (R/O) Time that this
package is in processor-specific C4 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
/**
Package. Package C6 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C6 Residency Counter. (R/O) Time that this
package is in processor-specific C6 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
#endif

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/** @file
MSR Definitions for Intel processors based on the Broadwell microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.
**/
#ifndef __BROADWELL_MSR_H__
#define __BROADWELL_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Broadwell microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3D || \
DisplayModel == 0x47 || \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)
/**
Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
Facilities.".
@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
@endcode
@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Ovf_PMC0.
///
UINT32 Ovf_PMC0:1;
///
/// [Bit 1] Ovf_PMC1.
///
UINT32 Ovf_PMC1:1;
///
/// [Bit 2] Ovf_PMC2.
///
UINT32 Ovf_PMC2:1;
///
/// [Bit 3] Ovf_PMC3.
///
UINT32 Ovf_PMC3:1;
UINT32 Reserved1:28;
///
/// [Bit 32] Ovf_FixedCtr0.
///
UINT32 Ovf_FixedCtr0:1;
///
/// [Bit 33] Ovf_FixedCtr1.
///
UINT32 Ovf_FixedCtr1:1;
///
/// [Bit 34] Ovf_FixedCtr2.
///
UINT32 Ovf_FixedCtr2:1;
UINT32 Reserved2:20;
///
/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
/// Addresses (ToPA).".
///
UINT32 Trace_ToPA_PMI:1;
UINT32 Reserved3:5;
///
/// [Bit 61] Ovf_Uncore.
///
UINT32 Ovf_Uncore:1;
///
/// [Bit 62] Ovf_BufDSSAVE.
///
UINT32 OvfBuf:1;
///
/// [Bit 63] CondChgd.
///
UINT32 CondChgd:1;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
@endcode
@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
/// processor-specific C-state code name (consuming the least power) for
/// the package. The default is set as factory-configured package C-state
/// limit. The following C-state code name encodings are supported: 0000b:
/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
///
UINT32 Limit:4;
UINT32 Reserved1:6;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
///
UINT32 IO_MWAIT:1;
UINT32 Reserved2:4;
///
/// [Bit 15] CFG Lock (R/WO).
///
UINT32 CFGLock:1;
UINT32 Reserved3:9;
///
/// [Bit 25] C3 State Auto Demotion Enable (R/W).
///
UINT32 C3AutoDemotion:1;
///
/// [Bit 26] C1 State Auto Demotion Enable (R/W).
///
UINT32 C1AutoDemotion:1;
///
/// [Bit 27] Enable C3 Undemotion (R/W).
///
UINT32 C3Undemotion:1;
///
/// [Bit 28] Enable C1 Undemotion (R/W).
///
UINT32 C1Undemotion:1;
///
/// [Bit 29] Enable Package C-State Auto-demotion (R/W).
///
UINT32 CStateAutoDemotion:1;
///
/// [Bit 30] Enable Package C-State Undemotion (R/W).
///
UINT32 CStateUndemotion:1;
UINT32 Reserved4:1;
UINT32 Reserved5:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
@endcode
@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
UINT32 Maximum1C:8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
UINT32 Maximum2C:8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
UINT32 Maximum3C:8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
UINT32 Maximum4C:8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5core active.
///
UINT32 Maximum5C:8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6core active.
///
UINT32 Maximum6C:8;
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
@endcode
@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639
#endif

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/** @file
MSR Definitions for Pentium M Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.
**/
#ifndef __PENTIUM_M_MSR_H__
#define __PENTIUM_M_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Pentium M Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0D \
) \
)
/**
See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
/**
See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
@endcode
@note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
/**
Processor Hard Power-On Configuration (R/W) Enables and disables processor
features. (R) Indicates current processor configuration.
@param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
/// Pentium M processor.
///
UINT32 DataErrorCheckingEnable:1;
///
/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
/// the Pentium M processor.
///
UINT32 ResponseErrorCheckingEnable:1;
///
/// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
UINT32 MCERR_DriveEnable:1;
///
/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
UINT32 AddressParityEnable:1;
UINT32 Reserved2:2;
///
/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
/// the Pentium M processor.
///
UINT32 BINIT_DriverEnable:1;
///
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 OutputTriStateEnable:1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 ExecuteBIST:1;
///
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
UINT32 MCERR_ObservationEnabled:1;
UINT32 Reserved3:1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
UINT32 BINIT_ObservationEnabled:1;
UINT32 Reserved4:1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
/// Always 0 on the Pentium M processor.
///
UINT32 ResetVector:1;
UINT32 Reserved5:1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
/// processor.
///
UINT32 APICClusterID:2;
///
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
/// 0 on the Pentium M processor.
///
UINT32 SystemBusFrequency:1;
UINT32 Reserved6:1;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
/// M processor.
///
UINT32 SymmetricArbitrationID:2;
///
/// [Bits 26:22] Clock Frequency Ratio (R/O).
///
UINT32 ClockFrequencyRatio:5;
UINT32 Reserved7:5;
UINT32 Reserved8:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
/**
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_n
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
@endcode
@note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
@{
**/
#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
/// @}
/**
Reserved.
@param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
**/
#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
/**
@param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
UINT32 L2HardwareEnabled:1;
UINT32 Reserved1:4;
///
/// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
/// cache data bus. ECC is always generated on write cycles. 1. = Disabled
/// (default) 2. = Enabled For the Pentium M processor, ECC checking on
/// the cache data bus is always enabled.
///
UINT32 ECCCheckEnable:1;
UINT32 Reserved2:2;
///
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
UINT32 L2Enabled:1;
UINT32 Reserved3:14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
UINT32 L2NotPresent:1;
UINT32 Reserved4:8;
UINT32 Reserved5:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
/**
@param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
///
UINT32 TM_SELECT:1;
UINT32 Reserved2:15;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
/**
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:3;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
/// this bit enables the thermal control circuit (TCC) portion of the
/// Intel Thermal Monitor feature. This allows processor clocks to be
/// automatically modulated based on the processor's thermal sensor
/// operation. 0 = Disabled (default). The automatic thermal control
/// circuit enable bit determines if the thermal control circuit (TCC)
/// will be activated when the processor's internal thermal sensor
/// determines the processor is about to exceed its maximum operating
/// temperature. When the TCC is activated and TM1 is enabled, the
/// processors clocks will be forced to a 50% duty cycle. BIOS must enable
/// this feature. The bit should not be confused with the on-demand
/// thermal control circuit enable bit.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
/// monitoring enabled 0 = Performance monitoring disabled.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:2;
///
/// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
/// processor to indicate a pending break event within the processor 0 =
/// Indicates compatible FERR# signaling behavior This bit must be set to
/// 1 to support XAPIC interrupt model usage.
/// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
/// support branch trace storage (BTS) 0 = BTS is supported
///
UINT32 FERR:1;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO)
/// 1 = Processor doesn't support branch trace storage (BTS)
/// 0 = BTS is supported
///
UINT32 BTS:1;
///
/// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
/// Processor does not support processor event based sampling (PEBS); 0 =
/// PEBS is supported. The Pentium M processor does not support PEBS.
///
UINT32 PEBS:1;
UINT32 Reserved5:3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
/// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
/// processor, this bit may be configured to be read-only.
///
UINT32 EIST:1;
UINT32 Reserved6:6;
///
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
/// disabled. xTPR messages are optional messages that allow the processor
/// to inform the chipset of its priority. The default is processor
/// specific.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
/**
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
to the MSR containing the most recent branch record. See also: -
MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
and Exception Recording (Pentium M Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
@endcode
@note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
/**
Debug Control (R/W) Controls how several debug features are used. Bit
definitions are discussed in the referenced section. See Section 17.13,
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
@endcode
@note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
**/
#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
/**
Last Exception Record To Linear IP (R) This area contains a pointer to the
target of the last branch instruction that the processor executed prior to
the last exception that was generated or the last interrupt that was
handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception
MSRs.".
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
@endcode
@note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
/**
Last Exception Record From Linear IP (R) Contains a pointer to the last
branch instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled. See Section
17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
@endcode
@note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
**/
#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
**/
#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear. When not implemented in the processor, all
reads and writes to this MSR will cause a general-protection exception.
@param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
**/
#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
**/
#define MSR_PENTIUM_M_MC3_CTL 0x00000410
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
**/
#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear. When not implemented in the processor, all
reads and writes to this MSR will cause a general-protection exception.
@param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
**/
#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
#endif

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/** @file
MSR Definitions for Pentium Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22.
**/
#ifndef __PENTIUM_MSR_H__
#define __PENTIUM_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Pentium Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x05 && \
( \
DisplayModel == 0x01 || \
DisplayModel == 0x02 || \
DisplayModel == 0x04 \
) \
)
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
@endcode
@note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
@endcode
@note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
/**
See Section 17.15, "Time-Stamp Counter.".
@param ECX MSR_PENTIUM_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
@endcode
@note MSR_PENTIUM_TSC is defined as TSC in SDM.
**/
#define MSR_PENTIUM_TSC 0x00000010
/**
See Section 18.24.1, "Control and Event Select Register (CESR).".
@param ECX MSR_PENTIUM_CESR (0x00000011)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
@endcode
@note MSR_PENTIUM_CESR is defined as CESR in SDM.
**/
#define MSR_PENTIUM_CESR 0x00000011
/**
Section 18.24.3, "Events Counted.".
@param ECX MSR_PENTIUM_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
@endcode
@note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
@{
**/
#define MSR_PENTIUM_CTR0 0x00000012
#define MSR_PENTIUM_CTR1 0x00000013
/// @}
#endif

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/** @file
MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.
**/
#ifndef __XEON_5600_MSR_H__
#define __XEON_5600_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor Series 5600?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x25 || \
DisplayModel == 0x2C \
) \
)
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
@endcode
@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
/// MSR, the configuration of AES instruction set availability is as
/// follows: 11b: AES instructions are not available until next RESET.
/// otherwise, AES instructions are available. Note, AES instruction set
/// is not available if read is unsuccessful. If the configuration is not
/// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
UINT32 AESConfiguration:2;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
/**
Thread. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
@endcode
@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
@endcode
@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
UINT32 Maximum1C:8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
UINT32 Maximum2C:8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
UINT32 Maximum3C:8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
UINT32 Maximum4C:8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5 core active.
///
UINT32 Maximum5C:8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6 core active.
///
UINT32 Maximum6C:8;
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
/**
Package. See Table 35-2.
@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
@endcode
@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
**/
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
#endif

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CloverEFI/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
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CloverEFI/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
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/** @file
MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
**/
#ifndef __XEON_E7_MSR_H__
#define __XEON_E7_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor E7 Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x2F \
) \
)
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
@endcode
@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
/// MSR, the configuration of AES instruction set availability is as
/// follows: 11b: AES instructions are not available until next RESET.
/// otherwise, AES instructions are available. Note, AES instruction set
/// is not available if read is unsuccessful. If the configuration is not
/// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
UINT32 AESConfiguration:2;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
/**
Thread. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
@endcode
@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7
/**
Package. Reserved Attempt to read/write will cause #UD.
@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
@endcode
@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
/**
Package. Uncore C-box 8 perfmon local box control MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
/**
Package. Uncore C-box 8 perfmon local box status MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
/**
Package. Uncore C-box 8 perfmon local box overflow control MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
/**
Package. Uncore C-box 8 perfmon event select MSR.
@param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
@{
**/
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
/// @}
/**
Package. Uncore C-box 8 perfmon counter MSR.
@param ECX MSR_XEON_E7_C8_PMON_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
@{
**/
#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
/// @}
/**
Package. Uncore C-box 9 perfmon local box control MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
/**
Package. Uncore C-box 9 perfmon local box status MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
/**
Package. Uncore C-box 9 perfmon local box overflow control MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
/**
Package. Uncore C-box 9 perfmon event select MSR.
@param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
@{
**/
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
/// @}
/**
Package. Uncore C-box 9 perfmon counter MSR.
@param ECX MSR_XEON_E7_C9_PMON_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
@{
**/
#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB
/// @}
#endif

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CloverEFI/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
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CloverEFI/UefiCpuPkg/Include/Register/SmramSaveStateMap.h
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/** @file
SMRAM Save State Map Definitions.
SMRAM Save State Map definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3C, Section 34.4 SMRAM
Volume 3C, Section 34.5 SMI Handler Execution Environment
Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __SMRAM_SAVE_STATE_MAP_H__
#define __SMRAM_SAVE_STATE_MAP_H__
///
/// Default SMBASE address
///
#define SMM_DEFAULT_SMBASE 0x30000
///
/// Offset of SMM handler from SMBASE
///
#define SMM_HANDLER_OFFSET 0x8000
///
/// Offset of SMRAM Save State Map from SMBASE
///
#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00
#pragma pack (1)
///
/// 32-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved[0x200]; // 7c00h
// Padded an extra 0x200 bytes so 32-bit and 64-bit
// SMRAM Save State Maps are the same size
UINT8 Reserved1[0xf8]; // 7e00h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved2[0x9C]; // 7f08h
UINT32 IOMemAddr; // 7fa0h
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS; // 7fach
UINT32 _SS; // 7fb0h
UINT32 _DS; // 7fb4h
UINT32 _FS; // 7fb8h
UINT32 _GS; // 7fbch
UINT32 Reserved3; // 7fc0h
UINT32 _TR; // 7fc4h
UINT32 _DR7; // 7fc8h
UINT32 _DR6; // 7fcch
UINT32 _EAX; // 7fd0h
UINT32 _ECX; // 7fd4h
UINT32 _EDX; // 7fd8h
UINT32 _EBX; // 7fdch
UINT32 _ESP; // 7fe0h
UINT32 _EBP; // 7fe4h
UINT32 _ESI; // 7fe8h
UINT32 _EDI; // 7fech
UINT32 _EIP; // 7ff0h
UINT32 _EFLAGS; // 7ff4h
UINT32 _CR3; // 7ff8h
UINT32 _CR0; // 7ffch
} SMRAM_SAVE_STATE_MAP32;
///
/// 64-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved1[0x1d0]; // 7c00h
UINT32 GdtBaseHiDword; // 7dd0h
UINT32 LdtBaseHiDword; // 7dd4h
UINT32 IdtBaseHiDword; // 7dd8h
UINT8 Reserved2[0xc]; // 7ddch
UINT64 IO_EIP; // 7de8h
UINT8 Reserved3[0x50]; // 7df0h
UINT32 _CR4; // 7e40h
UINT8 Reserved4[0x48]; // 7e44h
UINT32 GdtBaseLoDword; // 7e8ch
UINT32 Reserved5; // 7e90h
UINT32 IdtBaseLoDword; // 7e94h
UINT32 Reserved6; // 7e98h
UINT32 LdtBaseLoDword; // 7e9ch
UINT8 Reserved7[0x38]; // 7ea0h
UINT64 EptVmxControl; // 7ed8h
UINT32 EnEptVmxControl; // 7ee0h
UINT8 Reserved8[0x14]; // 7ee4h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved9[0x18]; // 7f04h
UINT64 _R15; // 7f1ch
UINT64 _R14;
UINT64 _R13;
UINT64 _R12;
UINT64 _R11;
UINT64 _R10;
UINT64 _R9;
UINT64 _R8;
UINT64 _RAX; // 7f5ch
UINT64 _RCX;
UINT64 _RDX;
UINT64 _RBX;
UINT64 _RSP;
UINT64 _RBP;
UINT64 _RSI;
UINT64 _RDI;
UINT64 IOMemAddr; // 7f9ch
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS;
UINT32 _SS;
UINT32 _DS;
UINT32 _FS;
UINT32 _GS;
UINT32 _LDTR; // 7fc0h
UINT32 _TR;
UINT64 _DR7; // 7fc8h
UINT64 _DR6;
UINT64 _RIP; // 7fd8h
UINT64 IA32_EFER; // 7fe0h
UINT64 _RFLAGS; // 7fe8h
UINT64 _CR3; // 7ff0h
UINT64 _CR0; // 7ff8h
} SMRAM_SAVE_STATE_MAP64;
///
/// Union of 32-bit and 64-bit SMRAM Save State Maps
///
typedef union {
SMRAM_SAVE_STATE_MAP32 x86;
SMRAM_SAVE_STATE_MAP64 x64;
} SMRAM_SAVE_STATE_MAP;
///
/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
///
#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004
///
/// SMRAM Save State Map IOMisc I/O Length Values
///
#define SMM_IO_LENGTH_BYTE 0x01
#define SMM_IO_LENGTH_WORD 0x02
#define SMM_IO_LENGTH_DWORD 0x04
///
/// SMRAM Save State Map IOMisc I/O Instruction Type Values
///
#define SMM_IO_TYPE_IN_IMMEDIATE 0x9
#define SMM_IO_TYPE_IN_DX 0x1
#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8
#define SMM_IO_TYPE_OUT_DX 0x0
#define SMM_IO_TYPE_INS 0x3
#define SMM_IO_TYPE_OUTS 0x2
#define SMM_IO_TYPE_REP_INS 0x7
#define SMM_IO_TYPE_REP_OUTS 0x6
///
/// SMRAM Save State Map IOMisc structure
///
typedef union {
struct {
UINT32 SmiFlag:1;
UINT32 Length:3;
UINT32 Type:4;
UINT32 Reserved1:8;
UINT32 Port:16;
} Bits;
UINT32 Uint32;
} SMRAM_SAVE_STATE_IOMISC;
#pragma pack ()
#endif

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CloverEFI/UefiCpuPkg/Include/Register/StmApi.h
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@ -1,954 +0,0 @@
/** @file
STM API definition
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_API_H_
#define _STM_API_H_
#include <Register/StmStatusCode.h>
#include <Register/StmResourceDescriptor.h>
#include <Register/ArchitecturalMsr.h>
#pragma pack (1)
/**
STM Header Structures
**/
typedef struct {
UINT32 Intel64ModeSupported :1; ///> bitfield
UINT32 EptSupported :1; ///> bitfield
UINT32 Reserved :30; ///> must be 0
} STM_FEAT;
#define STM_SPEC_VERSION_MAJOR 1
#define STM_SPEC_VERSION_MINOR 0
typedef struct {
UINT8 StmSpecVerMajor;
UINT8 StmSpecVerMinor;
///
/// Must be zero
///
UINT16 Reserved;
UINT32 StaticImageSize;
UINT32 PerProcDynamicMemorySize;
UINT32 AdditionalDynamicMemorySize;
STM_FEAT StmFeatures;
UINT32 NumberOfRevIDs;
UINT32 StmSmmRevID[1];
///
/// The total STM_HEADER should be 4K.
///
} SOFTWARE_STM_HEADER;
typedef struct {
MSEG_HEADER HwStmHdr;
SOFTWARE_STM_HEADER SwStmHdr;
} STM_HEADER;
/**
VMCALL API Numbers
API number convention: BIOS facing VMCALL interfaces have bit 16 clear
**/
/**
StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to
physical mapping of an address range into the SMM guest's virtual
memory space.
@param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)
@param EBX Low 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be 0.
@note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They
are not modified by StmMapAddressRange.
@retval CF 0
No error, EAX set to STM_SUCCESS.
The memory range was mapped as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested mapping contains a protected resource.
@retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED
The requested cache type could not be satisfied.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
Page count must not be zero.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmMapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_MAP_ADDRESS_RANGE 0x00000001
/**
STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 PhysicalAddress;
UINT64 VirtualAddress;
UINT32 PageCount;
UINT32 PatCacheType;
} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR
@{
**/
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF
/// @}
/**
StmUnmapAddressRange enables a SMM guest to remove mappings from its page
table.
If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can
control its own page tables. In this case, the STM implementation may
optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.
@param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)
@param EBX Low 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. The memory range was unmapped
as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmUnmapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002
/**
STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 VirtualAddress;
UINT32 Length;
} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Since the normal OS environment runs with a different set of page tables than
the SMM guest, virtual mappings will certainly be different. In order to do a
guest virtual to host physical translation of an address from the normal OS
code (EIP for example), it is necessary to walk the page tables governing the
OS page mappings. Since the SMM guest has no direct access to the page tables,
it must ask the STM to do this page table walk. This is supported via the
StmAddressLookup VMCALL. All OS page table formats need to be supported,
(e.g. PAE, PSE, Intel64, EPT, etc.)
StmAddressLookup takes a CR3 value and a virtual address from the interrupted
code as input and returns the corresponding physical address. It also
optionally maps the physical address into the SMM guest's virtual address
space. This new mapping persists ONLY for the duration of the SMI and if
needed in subsequent SMIs it must be remapped. PAT cache types follow the
interrupted environment's page table.
If EPT is enabled, OS CR3 only provides guest physical address information,
but the SMM guest might also need to know the host physical address. Since
SMM does not have direct access rights to EPT (it is protected by the STM),
SMM can input InterruptedEptp to let STM help to walk through it, and output
the host physical address.
@param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)
@param EBX Low 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. PhysicalAddress contains the
host physical address determined by walking the interrupted SMM
guest's page tables. SmmGuestVirtualAddress contains the SMM
guest's virtual mapping of the requested address.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested page was a protected page.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The requested virtual address did not exist in the page given
page table.
@retval EAX #ERROR_STM_BAD_CR3
The CR3 input was invalid. CR3 values must be from one of the
interrupted guest, or from the interrupted guest of another
processor.
@retval EAX #ERROR_STM_PHYSICAL_OVER_4G
The resulting physical address is greater than 4G and no virtual
address was supplied. The STM could not determine what address
within the SMM guest's virtual address space to do the mapping.
STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the
physical address determined by walking the interrupted
environment's page tables.
@retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL
A specific virtual mapping was requested, but
SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler
is running in 32 bit mode.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_ADDRESS_LOOKUP 0x00000003
/**
STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL
**/
typedef struct {
UINT64 InterruptedGuestVirtualAddress;
UINT32 Length;
UINT64 InterruptedCr3;
UINT64 InterruptedEptp;
UINT32 MapToSmmGuest:2;
UINT32 InterruptedCr4Pae:1;
UINT32 InterruptedCr4Pse:1;
UINT32 InterruptedIa32eMode:1;
UINT32 Reserved1:27;
UINT32 Reserved2;
UINT64 PhysicalAddress;
UINT64 SmmGuestVirtualAddress;
} STM_ADDRESS_LOOKUP_DESCRIPTOR;
/**
Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR
@{
**/
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3
/// @}
/**
When returning from a protection exception (see section 6.2), the SMM guest
can instruct the STM to take one of two paths. It can either request a value
be logged to the TXT.ERRORCODE register and subsequently reset the machine
(indicating it couldn't resolve the problem), or it can request that the STM
resume the SMM guest again with the specified register state.
Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more
like a jump or an IRET instruction than a "call". It does not return directly
to the caller, but indirectly to a different location specified on the
caller's stack (see section 6.2) or not at all.
If the SMM guest STM protection exception handler itself causes a protection
exception (e.g. a single nested exception), or more than 100 un-nested
exceptions occur within the scope of a single SMI event, the STM must write
STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and
assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify
the code requirements while still enabling a reasonable debugging capability.
@param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)
@param EBX If 0, resume SMM guest using register state found on exception
stack. If in range 0x01..0x0F, EBX contains a BIOS error code
which the STM must record in the TXT.ERRORCODE register and
subsequently reset the system via TXT.CMD.SYS_RESET. The value
of the TXT.ERRORCODE register is calculated as follows:
TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
Values 0x10..0xFFFFFFFF are reserved, do not use.
**/
#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004
/**
VMCALL API Numbers
API number convention: MLE facing VMCALL interfaces have bit 16 set.
The STM configuration lifecycle is as follows:
1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for
setup of initial protection profile. This is done on a single CPU and
has global effect.
3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial
protection profile. The protection profile is global across all CPUs.
4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving
SMI events. This must be done on every logical CPU.
5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or
#STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as
necessary.
6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked
following #STM_API_STOP VMCALL.
**/
/**
StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs
should remain disabled from the invocation of GETSEC[SENTER] until they are
re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is
enabled and the STM has been started and is active. Prior to invoking
StartStmVMCALL(), the MLE root should first invoke
InitializeProtectionVMCALL() followed by as many iterations of
ProtectResourceVMCALL() as necessary to establish the initial protection
profile. StartStmVmcall() must be invoked on all processor threads.
@param EAX #STM_API_START (0x00010001)
@param EDX STM configuration options. These provide the MLE with the
ability to pass configuration parameters to the STM.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been configured
and is now active and the guarding all requested resources.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. STM remains active and
guarding previously enabled resource list.
@retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED
The StartStmVMCALL() was invoked from VMX root mode, but outside
of SMX. This error code indicates the STM or platform does not
support the STM outside of SMX. The SMI handler remains active
and operates in legacy mode. See Appendix C
@retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT
The CPU doesn't support the MSR bit. The STM is not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_START (BIT16 | 1)
/**
Bit values for EDX input parameter to #STM_API_START VMCALL
@{
**/
#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0
/// @}
/**
The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is
normally done as part of a full teardown of the SMX environment when the
system is being shut down. At the time the call is invoked, SMI is enabled
and the STM is active. When the call returns, the STM has been stopped and
all STM context is discarded and SMI is disabled.
@param EAX #STM_API_STOP (0x00010002)
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been stopped and
is no longer processing SMI events. SMI is blocked.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_STOPPED
The STM was not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_STOP (BIT16 | 2)
/**
The ProtectResourceVMCALL() is invoked by the MLE root to request protection
of specific resources. The request is defined by a STM_RESOURCE_LIST, which
may contain more than one resource descriptor. Each resource descriptor is
processed separately by the STM. Whether or not protection for any specific
resource is granted is returned by the STM via the ReturnStatus bit in the
associated STM_RSC_DESC_HEADER.
@param EAX #STM_API_PROTECT_RESOURCE (0x00010003)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource request granted,
and clear for each resource request denied. There are no other fields
modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be
contained entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has successfully
merged the entire protection request into the active protection
profile. There is therefore no need to check the ReturnStatus
bits in the STM_RESOURCE_LIST.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE
At least one of the requested resource protections intersects a
BIOS required resource. Therefore, the caller must walk through
the STM_RESOURCE_LIST to determine which of the requested
resources was not granted protection. The entire list must be
traversed since there may be multiple failures.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources was not granted protection. The entire list
must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_OUT_OF_RESOURCES
The STM has encountered an internal error and cannot complete
the request.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_PROTECT_RESOURCE (BIT16 | 3)
/**
The UnProtectResourceVMCALL() is invoked by the MLE root to request that the
STM allow the SMI handler access to the specified resources.
@param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource processed. For
a properly formed STM_RESOURCE_LIST, this should be all resources
listed. There are no other fields modified by
UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained
entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The requested resources are
not being guarded by the STM.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources were not able to be unprotected. The entire
list must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)
/**
The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list
of BIOS required resources from the STM.
@param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)
@param EBX Low 32 bits of physical address of caller allocated destination
buffer. Bits 11:0 are ignored and assumed to be zero, making the
buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated destination
buffer.
@param EDX Indicates which page of the BIOS resource list to copy into the
destination buffer. The first page is indicated by 0, the second
page by 1, etc.
@retval CF 0
No error, EAX set to STM_SUCCESS. The destination buffer
contains the BIOS required resources. If the page retrieved is
the last page, EDX will be cleared to 0. If there are more pages
to retrieve, EDX is incremented to the next page index. Calling
software should iterate on GetBiosResourcesVMCALL() until EDX is
returned cleared to 0.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The page index supplied in EDX input was out of range.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@retval EDX Page index of next page to read. A return of EDX=0 signifies
that the entire list has been read.
@note EDX is both an input and an output register.
@note All other registers unmodified.
**/
#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)
/**
The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an
MLE guest (including the MLE root) from the list of protected domains.
@param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)
@param EBX Low 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to
be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST.
@note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not
modified by ManageVmcsDatabaseVMCALL().
@retval CF 0
No error, EAX set to STM_SUCCESS.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_INVALID_VMCS
Indicates a request to remove a VMCS from the database was made,
but the referenced VMCS was not found in the database.
@retval EAX #ERROR_STM_VMCS_PRESENT
Indicates a request to add a VMCS to the database was made, but
the referenced VMCS was already present in the database.
@retval EAX #ERROR_INVALID_PARAMETER
Indicates non-zero reserved field.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred
@note All other registers unmodified.
**/
#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)
/**
STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL
**/
typedef struct {
///
/// bits 11:0 are reserved and must be 0
///
UINT64 VmcsPhysPointer;
UINT32 DomainType :4;
UINT32 XStatePolicy :2;
UINT32 DegradationPolicy :4;
///
/// Must be 0
///
UINT32 Reserved1 :22;
UINT32 AddOrRemove;
} STM_VMCS_DATABASE_REQUEST;
/**
Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define DOMAIN_UNPROTECTED 0
#define DOMAIN_DISALLOWED_IO_OUT BIT0
#define DOMAIN_DISALLOWED_IO_IN BIT1
#define DOMAIN_INTEGRITY BIT2
#define DOMAIN_CONFIDENTIALITY BIT3
#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
/// @}
/**
Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define XSTATE_READWRITE 0x00
#define XSTATE_READONLY 0x01
#define XSTATE_SCRUB 0x03
/// @}
/**
Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define STM_VMCS_DATABASE_REQUEST_ADD 1
#define STM_VMCS_DATABASE_REQUEST_REMOVE 0
/// @}
/**
InitializeProtectionVMCALL() prepares the STM for setup of the initial
protection profile which is subsequently communicated via one or more
invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().
It is only necessary to invoke InitializeProtectionVMCALL() on one processor
thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked
or unmasked. The STM should return back to the MLE with "Blocking by SMI" set
to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the
MLE guest.
@param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)
@retval CF 0
No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM
capabilities as defined below. The STM has set up an empty
protection profile, except for the resources that it sets up to
protect itself. The STM must not allow the SMI handler to map
any pages from the MSEG Base to the top of TSEG. The STM must
also not allow SMI handler access to those MSRs which the STM
requires for its own protection.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. The STM remains active
and guarding the previously enabled resource list.
@retval EAX #ERROR_STM_UNPROTECTABLE
The STM determines that based on the platform configuration, the
STM is unable to protect itself. For example, the BIOS required
resource list contains memory pages in MSEG.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)
/**
Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION
@{
**/
#define STM_RSC_BGI BIT1
#define STM_RSC_BGM BIT2
#define STM_RSC_MSR BIT3
/// @}
/**
The ManageEventLogVMCALL() is invoked by the MLE root to control the logging
feature. It consists of several sub-functions to facilitate establishment of
the log itself, configuring what events will be logged, and functions to
start, stop, and clear the log.
@param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)
@param EBX Low 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and
assumed to be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST.
@retval CF=0
No error, EAX set to STM_SUCCESS.
@retval CF=1
An error occurred, EAX holds relevant error value. See subfunction
descriptions below for details.
@note All other registers unmodified.
**/
#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)
///
/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL
///
typedef struct {
UINT32 SubFunctionIndex;
union {
struct {
UINT32 PageCount;
//
// number of elements is PageCount
//
UINT64 Pages[];
} LogBuffer;
//
// bitmap of EVENT_TYPE
//
UINT32 EventEnableBitmap;
} Data;
} STM_EVENT_LOG_MANAGEMENT_REQUEST;
/**
Defines values for the SubFunctionIndex field of
#STM_EVENT_LOG_MANAGEMENT_REQUEST
@{
**/
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6
/// @}
/**
Log Entry Header
**/
typedef struct {
UINT32 EventSerialNumber;
UINT16 Type;
UINT16 Lock :1;
UINT16 Valid :1;
UINT16 ReadByMle :1;
UINT16 Wrapped :1;
UINT16 Reserved :12;
} LOG_ENTRY_HEADER;
/**
Enum values for the Type field of #LOG_ENTRY_HEADER
**/
typedef enum {
EvtLogStarted,
EvtLogStopped,
EvtLogInvalidParameterDetected,
EvtHandledProtectionException,
///
/// unhandled protection exceptions result in reset & cannot be logged
///
EvtBiosAccessToUnclaimedResource,
EvtMleResourceProtectionGranted,
EvtMleResourceProtectionDenied,
EvtMleResourceUnprotect,
EvtMleResourceUnprotectError,
EvtMleDomainTypeDegraded,
///
/// add more here
///
EvtMleMax,
///
/// Not used
///
EvtInvalid = 0xFFFFFFFF,
} EVENT_TYPE;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STARTED;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STOPPED;
typedef struct {
UINT32 VmcallApiNumber;
} ENTRY_EVT_LOG_INVALID_PARAM;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_DENIED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
typedef struct {
UINT64 VmcsPhysPointer;
UINT8 ExpectedDomainType;
UINT8 DegradedDomainType;
} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
typedef union {
ENTRY_EVT_LOG_STARTED Started;
ENTRY_EVT_LOG_STOPPED Stopped;
ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;
ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;
ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;
ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;
ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;
} LOG_ENTRY_DATA;
typedef struct {
LOG_ENTRY_HEADER Hdr;
LOG_ENTRY_DATA Data;
} STM_LOG_ENTRY;
/**
Maximum STM Log Entry Size
**/
#define STM_LOG_ENTRY_SIZE 256
/**
STM Protection Exception Stack Frame Structures
**/
typedef struct {
UINT32 Rdi;
UINT32 Rsi;
UINT32 Rbp;
UINT32 Rdx;
UINT32 Rcx;
UINT32 Rbx;
UINT32 Rax;
UINT32 Cr3;
UINT32 Cr2;
UINT32 Cr0;
UINT32 VmcsExitInstructionInfo;
UINT32 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT32 ErrorCode;
UINT32 Rip;
UINT32 Cs;
UINT32 Rflags;
UINT32 Rsp;
UINT32 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
typedef struct {
UINT64 R15;
UINT64 R14;
UINT64 R13;
UINT64 R12;
UINT64 R11;
UINT64 R10;
UINT64 R9;
UINT64 R8;
UINT64 Rdi;
UINT64 Rsi;
UINT64 Rbp;
UINT64 Rdx;
UINT64 Rcx;
UINT64 Rbx;
UINT64 Rax;
UINT64 Cr8;
UINT64 Cr3;
UINT64 Cr2;
UINT64 Cr0;
UINT64 VmcsExitInstructionInfo;
UINT64 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT64 ErrorCode;
UINT64 Rip;
UINT64 Cs;
UINT64 Rflags;
UINT64 Rsp;
UINT64 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
typedef union {
STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;
} STM_PROTECTION_EXCEPTION_STACK_FRAME;
/**
Enum values for the ErrorCode field in
#STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and
#STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
**/
typedef enum {
TxtSmmPageViolation = 1,
TxtSmmMsrViolation,
TxtSmmRegisterViolation,
TxtSmmIoViolation,
TxtSmmPciViolation
} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
/**
TXT Pocessor SMM Descriptor (PSD) structures
**/
typedef struct {
UINT64 SpeRip;
UINT64 SpeRsp;
UINT16 SpeSs;
UINT16 PageViolationException:1;
UINT16 MsrViolationException:1;
UINT16 RegisterViolationException:1;
UINT16 IoViolationException:1;
UINT16 PciViolationException:1;
UINT16 Reserved1:11;
UINT32 Reserved2;
} STM_PROTECTION_EXCEPTION_HANDLER;
typedef struct {
UINT8 ExecutionDisableOutsideSmrr:1;
UINT8 Intel64Mode:1;
UINT8 Cr4Pae : 1;
UINT8 Cr4Pse : 1;
UINT8 Reserved1 : 4;
} STM_SMM_ENTRY_STATE;
typedef struct {
UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint
UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request
UINT8 Reserved2 : 6;
} STM_SMM_RESUME_STATE;
typedef struct {
UINT8 DomainType : 4; ///> STM input to BIOS on each SMI
UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI
UINT8 EptEnabled : 1;
UINT8 Reserved3 : 1;
} STM_SMM_STATE;
#define TXT_SMM_PSD_OFFSET 0xfb00
#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0
typedef struct {
UINT64 Signature;
UINT16 Size;
UINT8 SmmDescriptorVerMajor;
UINT8 SmmDescriptorVerMinor;
UINT32 LocalApicId;
STM_SMM_ENTRY_STATE SmmEntryState;
STM_SMM_RESUME_STATE SmmResumeState;
STM_SMM_STATE StmSmmState;
UINT8 Reserved4;
UINT16 SmmCs;
UINT16 SmmDs;
UINT16 SmmSs;
UINT16 SmmOtherSegment;
UINT16 SmmTr;
UINT16 Reserved5;
UINT64 SmmCr3;
UINT64 SmmStmSetupRip;
UINT64 SmmStmTeardownRip;
UINT64 SmmSmiHandlerRip;
UINT64 SmmSmiHandlerRsp;
UINT64 SmmGdtPtr;
UINT32 SmmGdtSize;
UINT32 RequiredStmSmmRevId;
STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;
UINT64 Reserved6;
UINT64 BiosHwResourceRequirementsPtr;
// extend area
UINT64 AcpiRsdp;
UINT8 PhysicalAddressBits;
} TXT_PROCESSOR_SMM_DESCRIPTOR;
#pragma pack ()
#endif

228
CloverEFI/UefiCpuPkg/Include/Register/StmResourceDescriptor.h
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@ -1,228 +0,0 @@
/** @file
STM Resource Descriptor
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_RESOURCE_DESCRIPTOR_H_
#define _STM_RESOURCE_DESCRIPTOR_H_
#pragma pack (1)
/**
STM Resource Descriptor Header
**/
typedef struct {
UINT32 RscType;
UINT16 Length;
UINT16 ReturnStatus:1;
UINT16 Reserved:14;
UINT16 IgnoreResource:1;
} STM_RSC_DESC_HEADER;
/**
Define values for the RscType field of #STM_RSC_DESC_HEADER
@{
**/
#define END_OF_RESOURCES 0
#define MEM_RANGE 1
#define IO_RANGE 2
#define MMIO_RANGE 3
#define MACHINE_SPECIFIC_REG 4
#define PCI_CFG_RANGE 5
#define TRAPPED_IO_RANGE 6
#define ALL_RESOURCES 7
#define REGISTER_VIOLATION 8
#define MAX_DESC_TYPE 8
/// @}
/**
STM Resource End Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT64 ResourceListContinuation;
} STM_RSC_END;
/**
STM Resource Memory Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT64 Base;
UINT64 Length;
UINT32 RWXAttributes:3;
UINT32 Reserved:29;
UINT32 Reserved_2;
} STM_RSC_MEM_DESC;
/**
Define values for the RWXAttributes field of #STM_RSC_MEM_DESC
@{
**/
#define STM_RSC_MEM_R 0x1
#define STM_RSC_MEM_W 0x2
#define STM_RSC_MEM_X 0x4
/// @}
/**
STM Resource I/O Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT16 Base;
UINT16 Length;
UINT32 Reserved;
} STM_RSC_IO_DESC;
/**
STM Resource MMIO Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT64 Base;
UINT64 Length;
UINT32 RWXAttributes:3;
UINT32 Reserved:29;
UINT32 Reserved_2;
} STM_RSC_MMIO_DESC;
/**
Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC
@{
**/
#define STM_RSC_MMIO_R 0x1
#define STM_RSC_MMIO_W 0x2
#define STM_RSC_MMIO_X 0x4
/// @}
/**
STM Resource MSR Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT32 MsrIndex;
UINT32 KernelModeProcessing:1;
UINT32 Reserved:31;
UINT64 ReadMask;
UINT64 WriteMask;
} STM_RSC_MSR_DESC;
/**
STM PCI Device Path node used for the PciDevicePath field of
#STM_RSC_PCI_CFG_DESC
**/
typedef struct {
///
/// Must be 1, indicating Hardware Device Path
///
UINT8 Type;
///
/// Must be 1, indicating PCI
///
UINT8 Subtype;
///
/// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6
///
UINT16 Length;
UINT8 PciFunction;
UINT8 PciDevice;
} STM_PCI_DEVICE_PATH_NODE;
/**
STM Resource PCI Configuration Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT16 RWAttributes:2;
UINT16 Reserved:14;
UINT16 Base;
UINT16 Length;
UINT8 OriginatingBusNumber;
UINT8 LastNodeIndex;
STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];
} STM_RSC_PCI_CFG_DESC;
/**
Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC
@{
**/
#define STM_RSC_PCI_CFG_R 0x1
#define STM_RSC_PCI_CFG_W 0x2
/// @}
/**
STM Resource Trapped I/O Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT16 Base;
UINT16 Length;
UINT16 In:1;
UINT16 Out:1;
UINT16 Api:1;
UINT16 Reserved1:13;
UINT16 Reserved2;
} STM_RSC_TRAPPED_IO_DESC;
/**
STM Resource All Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
} STM_RSC_ALL_RESOURCES_DESC;
/**
STM Register Volation Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT32 RegisterType;
UINT32 Reserved;
UINT64 ReadMask;
UINT64 WriteMask;
} STM_REGISTER_VIOLATION_DESC;
/**
Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC
**/
typedef enum {
StmRegisterCr0,
StmRegisterCr2,
StmRegisterCr3,
StmRegisterCr4,
StmRegisterCr8,
StmRegisterMax,
} STM_REGISTER_VIOLATION_TYPE;
/**
Union of all STM resource types
**/
typedef union {
STM_RSC_DESC_HEADER Header;
STM_RSC_END End;
STM_RSC_MEM_DESC Mem;
STM_RSC_IO_DESC Io;
STM_RSC_MMIO_DESC Mmio;
STM_RSC_MSR_DESC Msr;
STM_RSC_PCI_CFG_DESC PciCfg;
STM_RSC_TRAPPED_IO_DESC TrappedIo;
STM_RSC_ALL_RESOURCES_DESC All;
STM_REGISTER_VIOLATION_DESC RegisterViolation;
} STM_RSC;
#pragma pack ()
#endif

78
CloverEFI/UefiCpuPkg/Include/Register/StmStatusCode.h
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@ -1,78 +0,0 @@
/** @file
STM Status Codes
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_STATUS_CODE_H_
#define _STM_STATUS_CODE_H_
/**
STM Status Codes
**/
typedef UINT32 STM_STATUS;
/**
Success code have BIT31 clear.
All error codes have BIT31 set.
STM errors have BIT16 set.
SMM errors have BIT17 set
Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set.
STM TXT.ERRORCODE codes have BIT30 set.
@{
**/
#define STM_SUCCESS 0x00000000
#define SMM_SUCCESS 0x00000000
#define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001)
#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002)
#define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003)
#define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004)
#define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005)
#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006)
#define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007)
#define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008)
#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED (BIT31 | BIT16 | 0x0009)
#define ERROR_STM_STOPPED (BIT31 | BIT16 | 0x000A)
#define ERROR_STM_BUFFER_TOO_SMALL (BIT31 | BIT16 | 0x000B)
#define ERROR_STM_INVALID_VMCS_DATABASE (BIT31 | BIT16 | 0x000C)
#define ERROR_STM_MALFORMED_RESOURCE_LIST (BIT31 | BIT16 | 0x000D)
#define ERROR_STM_INVALID_PAGECOUNT (BIT31 | BIT16 | 0x000E)
#define ERROR_STM_LOG_ALLOCATED (BIT31 | BIT16 | 0x000F)
#define ERROR_STM_LOG_NOT_ALLOCATED (BIT31 | BIT16 | 0x0010)
#define ERROR_STM_LOG_NOT_STOPPED (BIT31 | BIT16 | 0x0011)
#define ERROR_STM_LOG_NOT_STARTED (BIT31 | BIT16 | 0x0012)
#define ERROR_STM_RESERVED_BIT_SET (BIT31 | BIT16 | 0x0013)
#define ERROR_STM_NO_EVENTS_ENABLED (BIT31 | BIT16 | 0x0014)
#define ERROR_STM_OUT_OF_RESOURCES (BIT31 | BIT16 | 0x0015)
#define ERROR_STM_FUNCTION_NOT_SUPPORTED (BIT31 | BIT16 | 0x0016)
#define ERROR_STM_UNPROTECTABLE (BIT31 | BIT16 | 0x0017)
#define ERROR_STM_UNSUPPORTED_MSR_BIT (BIT31 | BIT16 | 0x0018)
#define ERROR_STM_UNSPECIFIED (BIT31 | BIT16 | 0xFFFF)
#define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
#define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
#define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
#define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
#define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
#define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
#define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
#define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
#define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
#define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
#define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
#define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
/// @}
#endif

44
CloverEFI/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
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@ -1,44 +0,0 @@
## @file
# This library defines some routines that are generic for IA32 family CPU
# to be UEFI specification compliant.
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseUefiCpuLib
FILE_GUID = 34C24FD7-7A90-45c2-89FD-946473D9CE98
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = UefiCpuLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources.IA32]
Ia32/InitializeFpu.asm
Ia32/InitializeFpu.S
[Sources.X64]
X64/InitializeFpu.asm
X64/InitializeFpu.S
[Packages]
MdePkg/MdePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
UefiCpuLib

73
CloverEFI/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
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@ -1,73 +0,0 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#*
#------------------------------------------------------------------------------
#
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
ASM_PFX(mMmxControlWord): .long 0x01F80
#
# Initializes floating point units for requirement of UEFI specification.
#
# This function initializes floating-point control word to 0x027F (all exceptions
# masked,double-precision, round-to-nearest) and multimedia-extensions control word
# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
# for masked underflow).
#
ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
pushl %ebx
#
# Initialize floating point units
#
finit
fldcw ASM_PFX(mFpuControlWord)
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
#
movl $1, %eax
cpuid
btl $25, %edx
jnc Done
#
# Set OSFXSR bit 9 in CR4
#
movl %cr4, %eax
or $0x200, %eax
movl %eax, %cr4
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction
#
ldmxcsr ASM_PFX(mMmxControlWord)
Done:
popl %ebx
ret
#END

57
CloverEFI/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
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@ -1,57 +0,0 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#*
#------------------------------------------------------------------------------
#
# Initializes floating point units for requirement of UEFI specification.
#
# This function initializes floating-point control word to 0x027F (all exceptions
# masked,double-precision, round-to-nearest) and multimedia-extensions control word
# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
# for masked underflow).
#
ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
#
# Initialize floating point units
#
finit
#
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
pushq $0x027F
lea (%rsp), %rax
fldcw (%rax)
popq %rax
#
# Set OSFXSR bit 9 in CR4
#
movq %cr4, %rax
or $0x200, %rax
movq %rax, %cr4
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
pushq $0x01F80
lea (%rsp), %rax
ldmxcsr (%rax)
popq %rax
ret

62
CloverEFI/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
View File

@ -1,62 +0,0 @@
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
;* This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;*
;------------------------------------------------------------------------------
.const
;
; Float control word initial value:
; all exceptions masked, double-precision, round-to-nearest
;
mFpuControlWord DW 027Fh
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
mMmxControlWord DD 01F80h
.code
;
; Initializes floating point units for requirement of UEFI specification.
;
; This function initializes floating-point control word to 0x027F (all exceptions
; masked,double-precision, round-to-nearest) and multimedia-extensions control word
; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
; for masked underflow).
;
InitializeFloatingPointUnits PROC PUBLIC
;
; Initialize floating point units
;
; The following opcodes stand for instruction 'finit'
; to be supported by some 64-bit assemblers
;
DB 9Bh, 0DBh, 0E3h
fldcw mFpuControlWord
;
; Set OSFXSR bit 9 in CR4
;
mov rax, cr4
or rax, BIT9
mov cr4, rax
ldmxcsr mMmxControlWord
ret
InitializeFloatingPointUnits ENDP
END

754
CloverEFI/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@ -1,754 +0,0 @@
/** @file
Local APIC Library.
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Register/LocalApic.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/LocalApicLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
#include <Library/PcdLib.h>
//
// Library internal functions
//
/**
Read from a local APIC register.
This function reads from a local APIC register either in xAPIC or x2APIC mode.
It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
accessed using multiple 32-bit loads or stores, so this function only performs
32-bit read.
@param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
It must be 16-byte aligned.
@return 32-bit Value read from the register.
**/
UINT32
EFIAPI
ReadLocalApicReg (
IN UINTN MmioOffset
)
{
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
}
/**
Write to a local APIC register.
This function writes to a local APIC register either in xAPIC or x2APIC mode.
It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
accessed using multiple 32-bit loads or stores, so this function only performs
32-bit write.
if the register index is invalid or unsupported in current APIC mode, then ASSERT.
@param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
It must be 16-byte aligned.
@param Value Value to be written to the register.
**/
VOID
EFIAPI
WriteLocalApicReg (
IN UINTN MmioOffset,
IN UINT32 Value
)
{
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
}
/**
Send an IPI by writing to ICR.
This function returns after the IPI has been accepted by the target processor.
@param IcrLow 32-bit value to be written to the low half of ICR.
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
**/
VOID
SendIpi (
IN UINT32 IcrLow,
IN UINT32 ApicId
)
{
LOCAL_APIC_ICR_LOW IcrLowReg;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
ASSERT (ApicId <= 0xff);
//
// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
//
WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
do {
IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
} while (IcrLowReg.Bits.DeliveryStatus != 0);
}
//
// Library API implementation functions
//
/**
Get the current local APIC mode.
If local APIC is disabled, then ASSERT.
@retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
@retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
**/
UINTN
EFIAPI
GetApicMode (
VOID
)
{
DEBUG_CODE (
{
MSR_IA32_APIC_BASE ApicBaseMsr;
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
//
// Local APIC should have been enabled
//
ASSERT (ApicBaseMsr.Bits.En != 0);
ASSERT (ApicBaseMsr.Bits.Extd == 0);
}
);
return LOCAL_APIC_MODE_XAPIC;
}
/**
Set the current local APIC mode.
If the specified local APIC mode is not valid, then ASSERT.
If the specified local APIC mode can't be set as current, then ASSERT.
@param ApicMode APIC mode to be set.
**/
VOID
EFIAPI
SetApicMode (
IN UINTN ApicMode
)
{
ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
}
/**
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
the 32-bit local APIC ID is returned as initial APIC ID.
@return 32-bit initial local APIC ID of the executing processor.
**/
UINT32
EFIAPI
GetInitialApicId (
VOID
)
{
UINT32 RegEbx;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
return RegEbx >> 24;
}
/**
Get the local APIC ID of the executing processor.
@return 32-bit local APIC ID of the executing processor.
**/
UINT32
EFIAPI
GetApicId (
VOID
)
{
UINT32 ApicId;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId >>= 24;
return ApicId;
}
/**
Get the value of the local APIC version register.
@return the value of the local APIC version register.
**/
UINT32
EFIAPI
GetApicVersion (
VOID
)
{
return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
}
/**
Send a Fixed IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId The local APIC ID of the target processor.
@param Vector The vector number of the interrupt being sent.
**/
VOID
EFIAPI
SendFixedIpi (
IN UINT32 ApicId,
IN UINT8 Vector
)
{
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1;
IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, ApicId);
}
/**
Send a Fixed IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
@param Vector The vector number of the interrupt being sent.
**/
VOID
EFIAPI
SendFixedIpiAllExcludingSelf (
IN UINT8 Vector
)
{
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, 0);
}
/**
Send a SMI IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
VOID
EFIAPI
SendSmiIpi (
IN UINT32 ApicId
)
{
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
/**
Send a SMI IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
**/
VOID
EFIAPI
SendSmiIpiAllExcludingSelf (
VOID
)
{
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
/**
Send an INIT IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
VOID
EFIAPI
SendInitIpi (
IN UINT32 ApicId
)
{
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
/**
Send an INIT IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
**/
VOID
EFIAPI
SendInitIpiAllExcludingSelf (
VOID
)
{
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@param ApicId Specify the local APIC ID of the target processor.
@param StartupRoutine Points to a start-up routine which is below 1M physical
address and 4K aligned.
**/
VOID
EFIAPI
SendInitSipiSipi (
IN UINT32 ApicId,
IN UINT32 StartupRoutine
)
{
LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId);
MicroSecondDelay (10);
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
MicroSecondDelay (200);
SendIpi (IcrLow.Uint32, ApicId);
}
/**
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@param StartupRoutine Points to a start-up routine which is below 1M physical
address and 4K aligned.
**/
VOID
EFIAPI
SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine
)
{
LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf ();
MicroSecondDelay (10);
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
MicroSecondDelay (200);
SendIpi (IcrLow.Uint32, 0);
}
/**
Programming Virtual Wire Mode.
This function programs the local APIC for virtual wire mode following
the example described in chapter A.3 of the MP 1.4 spec.
IOxAPIC is not involved in this type of virtual wire mode.
**/
VOID
EFIAPI
ProgramVirtualWireMode (
VOID
)
{
LOCAL_APIC_SVR Svr;
LOCAL_APIC_LVT_LINT Lint;
//
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
//
Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SpuriousVector = 0xf;
Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
//
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
//
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
//
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
//
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
}
/**
Disable LINT0 & LINT1 interrupts.
This function sets the mask flag in the LVT LINT0 & LINT1 registers.
**/
VOID
EFIAPI
DisableLvtInterrupts (
VOID
)
{
LOCAL_APIC_LVT_LINT LvtLint;
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
}
/**
Read the initial count value from the init-count register.
@return The initial count value read from the init-count register.
**/
UINT32
EFIAPI
GetApicTimerInitCount (
VOID
)
{
return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
}
/**
Read the current count value from the current-count register.
@return The current count value read from the current-count register.
**/
UINT32
EFIAPI
GetApicTimerCurrentCount (
VOID
)
{
return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
}
/**
Initialize the local APIC timer.
The local APIC timer is initialized and enabled.
@param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
If it is 0, then use the current divide value in the DCR.
@param InitCount The initial count value.
@param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
@param Vector The timer interrupt vector number.
**/
VOID
EFIAPI
InitializeApicTimer (
IN UINTN DivideValue,
IN UINT32 InitCount,
IN BOOLEAN PeriodicMode,
IN UINT8 Vector
)
{
LOCAL_APIC_SVR Svr;
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor;
//
// Ensure local APIC is in software-enabled state.
//
Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
//
// Program init-count register.
//
WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
if (DivideValue != 0) {
ASSERT (DivideValue <= 128);
ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
}
//
// Enable APIC timer interrupt with specified timer mode.
//
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode) {
LvtTimer.Bits.TimerMode = 1;
} else {
LvtTimer.Bits.TimerMode = 0;
}
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
/**
Get the state of the local APIC timer.
@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
@param Vector Return the timer interrupt vector number.
**/
VOID
EFIAPI
GetApicTimerState (
OUT UINTN *DivideValue OPTIONAL,
OUT BOOLEAN *PeriodicMode OPTIONAL,
OUT UINT8 *Vector OPTIONAL
)
{
UINT32 Divisor;
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
if (DivideValue != NULL) {
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
Divisor = (Divisor + 1) & 0x7;
*DivideValue = ((UINTN)1) << Divisor;
}
if (PeriodicMode != NULL || Vector != NULL) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) {
*PeriodicMode = TRUE;
} else {
*PeriodicMode = FALSE;
}
}
if (Vector != NULL) {
*Vector = (UINT8) LvtTimer.Bits.Vector;
}
}
}
/**
Enable the local APIC timer interrupt.
**/
VOID
EFIAPI
EnableApicTimerInterrupt (
VOID
)
{
LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
/**
Disable the local APIC timer interrupt.
**/
VOID
EFIAPI
DisableApicTimerInterrupt (
VOID
)
{
LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
/**
Get the local APIC timer interrupt state.
@retval TRUE The local APIC timer interrupt is enabled.
@retval FALSE The local APIC timer interrupt is disabled.
**/
BOOLEAN
EFIAPI
GetApicTimerInterruptState (
VOID
)
{
LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
}
/**
Send EOI to the local APIC.
**/
VOID
EFIAPI
SendApicEoi (
VOID
)
{
WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
}
/**
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
UINT32
EFIAPI
GetApicMsiAddress (
VOID
)
{
LOCAL_APIC_MSI_ADDRESS MsiAddress;
//
// Return address for an MSI interrupt to be delivered only to the APIC ID
// of the currently executing processor.
//
MsiAddress.Uint32 = 0;
MsiAddress.Bits.BaseAddress = 0xFEE;
MsiAddress.Bits.DestinationId = GetApicId ();
return MsiAddress.Uint32;
}
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
2: LOCAL_APIC_DELIVERY_MODE_SMI
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
UINT64
EFIAPI
GetApicMsiValue (
IN UINT8 Vector,
IN UINTN DeliveryMode,
IN BOOLEAN LevelTriggered,
IN BOOLEAN AssertionLevel
)
{
LOCAL_APIC_MSI_DATA MsiData;
ASSERT (Vector >= 0x10 && Vector <= 0xFE);
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
MsiData.Uint64 = 0;
MsiData.Bits.Vector = Vector;
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
if (LevelTriggered) {
MsiData.Bits.TriggerMode = 1;
if (AssertionLevel) {
MsiData.Bits.Level = 1;
}
}
return MsiData.Uint64;
}

46
CloverEFI/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
View File

@ -1,46 +0,0 @@
## @file
# Component description file for CPU Local APIC Library.
#
# This library instance supports xAPIC mode only.
#
# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseXApicLib
FILE_GUID = D87CA0A8-1AC2-439b-90F8-EF4A2AC88DAF
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = LocalApicLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
BaseXApicLib.c
[Packages]
MdePkg/MdePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseLib
DebugLib
TimerLib
IoLib
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress

47
CloverEFI/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
View File

@ -1,47 +0,0 @@
## @file
# Component description file for CPU Local APIC Library.
#
# This library instance supports x2APIC capable processors
# which have xAPIC and x2APIC modes.
#
# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseXApicX2ApicLib
FILE_GUID = 967B6E05-F10D-4c10-8BF7-365291CA143F
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = LocalApicLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
BaseXApicX2ApicLib.c
[Packages]
MdePkg/MdePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseLib
DebugLib
TimerLib
IoLib
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress

173
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
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/** @file
CPU Exception Handler Library common functions.
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuExceptionCommon.h"
//
// Error code flag indicating whether or not an error code will be
// pushed on the stack if an exception occurs.
//
// 1 means an error code will be pushed, otherwise 0
//
CONST UINT32 mErrorCodeFlag = 0x00027d00;
RESERVED_VECTORS_DATA *mReservedVectors = NULL;
//
// Define the maximum message length
//
#define MAX_DEBUG_MESSAGE_LENGTH 0x100
/**
Prints a message to the serial port.
@param Format Format string for the message to print.
@param ... Variable argument list whose contents are accessed
based on the format string specified by Format.
**/
VOID
EFIAPI
InternalPrintMessage (
IN CONST CHAR8 *Format,
...
)
{
CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
VA_LIST Marker;
//
// Convert the message to an ASCII String
//
VA_START (Marker, Format);
AsciiVSPrint (Buffer, sizeof (Buffer), Format, Marker);
VA_END (Marker);
//
// Send the print string to a Serial Port
//
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen(Buffer));
}
/**
Find and display image base address and return image base and its entry point.
@param CurrentEip Current instruction pointer.
@param EntryPoint Return module entry point if module header is found.
@return !0 Image base address.
@return 0 Image header cannot be found.
**/
UINTN
FindModuleImageBase (
IN UINTN CurrentEip,
OUT UINTN *EntryPoint
)
{
UINTN Pe32Data;
EFI_IMAGE_DOS_HEADER *DosHdr;
EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
VOID *PdbPointer;
//
// Find Image Base
//
Pe32Data = CurrentEip & ~(mImageAlignSize - 1);
while (Pe32Data != 0) {
DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
//
// DOS image header is present, so read the PE header after the DOS image header.
//
Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));
//
// Make sure PE header address does not overflow and is less than the initial address.
//
if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CurrentEip)) {
if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
//
// It's PE image.
//
InternalPrintMessage ("!!!! Find PE image ");
*EntryPoint = (UINTN)Pe32Data + (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff);
break;
}
}
} else {
//
// DOS image header is not present, TE header is at the image base.
//
Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || Hdr.Te->Machine == IMAGE_FILE_MACHINE_X64)) {
//
// It's TE image, it TE header and Machine type match
//
InternalPrintMessage ("!!!! Find TE image ");
*EntryPoint = (UINTN)Pe32Data + (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize;
break;
}
}
//
// Not found the image base, check the previous aligned address
//
Pe32Data -= mImageAlignSize;
}
if (Pe32Data != 0) {
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
if (PdbPointer != NULL) {
InternalPrintMessage ("%a", PdbPointer);
} else {
InternalPrintMessage ("(No PDB) " );
}
} else {
InternalPrintMessage ("!!!! Can't find image information. !!!!\n");
}
return Pe32Data;
}
/**
Read and save reserved vector information
@param[in] VectorInfo Pointer to reserved vector list.
@param[out] ReservedVector Pointer to reserved vector data buffer.
@param[in] VectorCount Vector number to be updated.
@return EFI_SUCCESS Read and save vector info successfully.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
**/
EFI_STATUS
ReadAndVerifyVectorInfo (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
OUT RESERVED_VECTORS_DATA *ReservedVector,
IN UINTN VectorCount
)
{
while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
if (VectorInfo->Attribute > EFI_VECTOR_HANDOFF_HOOK_AFTER) {
//
// If vector attrubute is invalid
//
return EFI_INVALID_PARAMETER;
}
if (VectorInfo->VectorNumber < VectorCount) {
ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;
}
VectorInfo ++;
}
return EFI_SUCCESS;
}

242
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
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@ -1,242 +0,0 @@
/** @file
Common header file for CPU Exception Handler Library.
Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _CPU_EXCEPTION_COMMON_H_
#define _CPU_EXCEPTION_COMMON_H_
#include <Ppi/VectorHandoffInfo.h>
#include <Protocol/Cpu.h>
#include <Library/BaseLib.h>
#include <Library/SerialPortLib.h>
#include <Library/PrintLib.h>
#include <Library/LocalApicLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/SynchronizationLib.h>
#define CPU_EXCEPTION_NUM 32
#define CPU_INTERRUPT_NUM 256
#define HOOKAFTER_STUB_SIZE 16
#include "ArchInterruptDefs.h"
//
// Record exception handler information
//
typedef struct {
UINTN ExceptionStart;
UINTN ExceptionStubHeaderSize;
UINTN HookAfterStubHeaderStart;
} EXCEPTION_HANDLER_TEMPLATE_MAP;
extern CONST UINT32 mErrorCodeFlag;
extern CONST UINTN mImageAlignSize;
extern CONST UINTN mDoFarReturnFlag;
extern RESERVED_VECTORS_DATA *mReservedVectors;
/**
Return address map of exception handler template so that C code can generate
exception tables.
@param AddressMap Pointer to a buffer where the address map is returned.
**/
VOID
EFIAPI
AsmGetTemplateAddressMap (
OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
);
/**
Return address map of exception handler template so that C code can generate
exception tables.
@param IdtEntry Pointer to IDT entry to be updated.
@param InterruptHandler IDT handler value.
**/
VOID
ArchUpdateIdtEntry (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
IN UINTN InterruptHandler
);
/**
Read IDT handler value from IDT entry.
@param IdtEntry Pointer to IDT entry to be read.
**/
UINTN
ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
);
/**
Prints a message to the serial port.
@param Format Format string for the message to print.
@param ... Variable argument list whose contents are accessed
based on the format string specified by Format.
**/
VOID
EFIAPI
InternalPrintMessage (
IN CONST CHAR8 *Format,
...
);
/**
Find and display image base address and return image base and its entry point.
@param CurrentEip Current instruction pointer.
@param EntryPoint Return module entry point if module header is found.
@return !0 Image base address.
@return 0 Image header cannot be found.
**/
UINTN
FindModuleImageBase (
IN UINTN CurrentEip,
OUT UINTN *EntryPoint
);
/**
Display CPU information.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
DumpCpuContent (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
Internal worker function to initialize exception handler.
@param[in] VectorInfo Pointer to reserved vector list.
@retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
with default exception handlers.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
@retval EFI_UNSUPPORTED This function is not supported.
**/
EFI_STATUS
InitializeCpuExceptionHandlersWorker (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
);
/**
Registers a function to be called from the processor interrupt handler.
@param[in] InterruptType Defines which interrupt or exception to hook.
@param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
when a processor interrupt occurs. If this parameter is NULL, then the handler
will be uninstalled.
@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
previously installed.
@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
previously installed.
@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
or this function is not supported.
**/
EFI_STATUS
RegisterCpuInterruptHandlerWorker (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
/**
Internal worker function to update IDT entries accordling to vector attributes.
@param[in] IdtTable Pointer to IDT table.
@param[in] TemplateMap Pointer to a buffer where the address map is returned.
@param[in] IdtEntryCount IDT entries number to be updated.
**/
VOID
UpdateIdtTable (
IN IA32_IDT_GATE_DESCRIPTOR *IdtTable,
IN EXCEPTION_HANDLER_TEMPLATE_MAP *TemplateMap,
IN UINTN IdtEntryCount
);
/**
Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
@param[in] ExceptionType Exception type.
@param[in] SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
ArchSaveExceptionContext (
IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
@param[in] ExceptionType Exception type.
@param[in] SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
ArchRestoreExceptionContext (
IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
Fix up the vector number in the vector code.
@param[in] VectorBase Base address of the vector handler.
@param[in] VectorNum Index of vector.
@param[in] HookStub TRUE HookAfterStubHeaderEnd.
FALSE HookAfterStubHeaderEnd
**/
VOID
EFIAPI
AsmVectorNumFixup (
IN VOID *VectorBase,
IN UINT8 VectorNum,
IN BOOLEAN HookStub
);
/**
Read and save reserved vector information
@param[in] VectorInfo Pointer to reserved vector list.
@param[out] ReservedVector Pointer to reserved vector data buffer.
@param[in] VectorCount Vector number to be updated.
@return EFI_SUCCESS Read and save vector info successfully.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
**/
EFI_STATUS
ReadAndVerifyVectorInfo (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
OUT RESERVED_VECTORS_DATA *ReservedVector,
IN UINTN VectorCount
);
#endif

BIN
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni
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170
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
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/** @file
CPU exception handler library implemenation for DXE modules.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include "CpuExceptionCommon.h"
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
CONST UINTN mDoFarReturnFlag = 0;
extern SPIN_LOCK mDisplayMessageSpinLock;
extern EFI_CPU_INTERRUPT_HANDLER *mExternalInterruptHandler;
/**
Initializes all CPU exceptions entries and provides the default exception handlers.
Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
@param[in] VectorInfo Pointer to reserved vector list.
@retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
with default exception handlers.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
@retval EFI_UNSUPPORTED This function is not supported.
**/
EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
return InitializeCpuExceptionHandlersWorker (VectorInfo);
}
/**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
@param[in] VectorInfo Pointer to reserved vector list.
@retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized
with default interrupt/exception handlers.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
@retval EFI_UNSUPPORTED This function is not supported.
**/
EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
EFI_STATUS Status;
IA32_IDT_GATE_DESCRIPTOR *IdtTable;
IA32_DESCRIPTOR IdtDescriptor;
UINTN IdtEntryCount;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
UINTN Index;
UINTN InterruptEntry;
UINT8 *InterruptEntryCode;
mReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM);
ASSERT (mReservedVectors != NULL);
SetMem((VOID *) mReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);
if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, mReservedVectors, CPU_INTERRUPT_NUM);
if (EFI_ERROR(Status)) {
FreePool(mReservedVectors);
return EFI_INVALID_PARAMETER;
}
}
InitializeSpinLock (&mDisplayMessageSpinLock);
mExternalInterruptHandler = AllocateZeroPool(sizeof (EFI_CPU_INTERRUPT_HANDLER) * CPU_INTERRUPT_NUM);
ASSERT (mExternalInterruptHandler != NULL);
//
// Read IDT descriptor and calculate IDT size
//
AsmReadIdtr (&IdtDescriptor);
IdtEntryCount = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
if (IdtEntryCount > CPU_INTERRUPT_NUM) {
IdtEntryCount = CPU_INTERRUPT_NUM;
}
//
// Create Interrupt Descriptor Table and Copy the old IDT table in
//
IdtTable = AllocateZeroPool(sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM);
ASSERT (IdtTable != NULL);
CopyMem(IdtTable, (VOID *)IdtDescriptor.Base, sizeof (IA32_IDT_GATE_DESCRIPTOR) * IdtEntryCount);
AsmGetTemplateAddressMap (&TemplateMap);
ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
InterruptEntryCode = AllocatePool (TemplateMap.ExceptionStubHeaderSize * CPU_INTERRUPT_NUM);
ASSERT (InterruptEntryCode != NULL);
InterruptEntry = (UINTN) InterruptEntryCode;
for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) {
CopyMem(
(VOID *) InterruptEntry,
(VOID *) TemplateMap.ExceptionStart,
TemplateMap.ExceptionStubHeaderSize
);
AsmVectorNumFixup ((VOID *) InterruptEntry, (UINT8) Index, FALSE);
InterruptEntry += TemplateMap.ExceptionStubHeaderSize;
}
TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode;
UpdateIdtTable (IdtTable, &TemplateMap, CPU_INTERRUPT_NUM);
//
// Load Interrupt Descriptor Table
//
IdtDescriptor.Base = (UINTN) IdtTable;
IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor);
return EFI_SUCCESS;
}
/**
Registers a function to be called from the processor interrupt handler.
This function registers and enables the handler specified by InterruptHandler for a processor
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
The installed handler is called once for each processor interrupt or exception.
NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
@param[in] InterruptType Defines which interrupt or exception to hook.
@param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
when a processor interrupt occurs. If this parameter is NULL, then the handler
will be uninstalled.
@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
previously installed.
@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
previously installed.
@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
or this function is not supported.
**/
EFI_STATUS
EFIAPI
RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler);
}

288
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeSmmCpuException.c
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@ -1,288 +0,0 @@
/** @file
CPU Exception Library provides DXE/SMM CPU common exception handler.
Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuExceptionCommon.h"
#include <Library/DebugLib.h>
//
// Spinlock for CPU information display
//
SPIN_LOCK mDisplayMessageSpinLock;
//
// Image align size for DXE/SMM
//
CONST UINTN mImageAlignSize = SIZE_4KB;
RESERVED_VECTORS_DATA mReservedVectorsData[CPU_INTERRUPT_NUM];
EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_INTERRUPT_NUM];
EFI_CPU_INTERRUPT_HANDLER *mExternalInterruptHandler = NULL;
UINTN mEnabledInterruptNum = 0;
/**
Common exception handler.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
EFIAPI
CommonExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext;
ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32);
switch (mReservedVectors[ExceptionType].Attribute) {
case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
//
// Need to jmp to old IDT handler after this exception handler
//
ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
ExceptionHandlerContext->OldIdtHandler = mReservedVectors[ExceptionType].ExceptonHandler;
break;
case EFI_VECTOR_HANDOFF_HOOK_AFTER:
while (TRUE) {
//
// If if anyone has gotten SPIN_LOCK for owner running hook after
//
if (AcquireSpinLockOrFail (&mReservedVectors[ExceptionType].SpinLock)) {
//
// Need to execute old IDT handler before running this exception handler
//
mReservedVectors[ExceptionType].ApicId = GetApicId ();
ArchSaveExceptionContext (ExceptionType, SystemContext);
ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
ExceptionHandlerContext->OldIdtHandler = mReservedVectors[ExceptionType].ExceptonHandler;
return;
}
//
// If failed to acquire SPIN_LOCK, check if it was locked by processor itself
//
if (mReservedVectors[ExceptionType].ApicId == GetApicId ()) {
//
// Old IDT handler has been executed, then retore CPU exception content to
// run new exception handler.
//
ArchRestoreExceptionContext (ExceptionType, SystemContext);
//
// Rlease spin lock for ApicId
//
ReleaseSpinLock (&mReservedVectors[ExceptionType].SpinLock);
break;
}
CpuPause ();
}
break;
case 0xffffffff:
break;
default:
//
// It should never reach here
//
CpuDeadLoop ();
break;
}
if (mExternalInterruptHandler[ExceptionType] != NULL) {
(mExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);
} else if (ExceptionType < CPU_EXCEPTION_NUM) {
//
// Get Spinlock to display CPU information
//
while (!AcquireSpinLockOrFail (&mDisplayMessageSpinLock)) {
CpuPause ();
}
//
// Display ExceptionType, CPU information and Image information
//
DumpCpuContent (ExceptionType, SystemContext);
//
// Release Spinlock of output message
//
ReleaseSpinLock (&mDisplayMessageSpinLock);
//
// Enter a dead loop if needn't to execute old IDT handler further
//
if (mReservedVectors[ExceptionType].Attribute != EFI_VECTOR_HANDOFF_HOOK_BEFORE) {
CpuDeadLoop ();
}
}
}
/**
Internal worker function to update IDT entries accordling to vector attributes.
@param[in] IdtTable Pointer to IDT table.
@param[in] TemplateMap Pointer to a buffer where the address map is returned.
@param[in] IdtEntryCount IDT entries number to be updated.
**/
VOID
UpdateIdtTable (
IN IA32_IDT_GATE_DESCRIPTOR *IdtTable,
IN EXCEPTION_HANDLER_TEMPLATE_MAP *TemplateMap,
IN UINTN IdtEntryCount
)
{
UINT16 CodeSegment;
UINTN Index;
UINTN InterruptHandler;
//
// Use current CS as the segment selector of interrupt gate in IDT
//
CodeSegment = AsmReadCs ();
for (Index = 0; Index < IdtEntryCount; Index ++) {
IdtTable[Index].Bits.Selector = CodeSegment;
//
// Check reserved vectors attributes
//
switch (mReservedVectors[Index].Attribute) {
case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:
//
// Keep original IDT entry
//
continue;
case EFI_VECTOR_HANDOFF_HOOK_AFTER:
InitializeSpinLock (&mReservedVectors[Index].SpinLock);
CopyMem(
(VOID *) mReservedVectors[Index].HookAfterStubHeaderCode,
(VOID *) TemplateMap->HookAfterStubHeaderStart,
TemplateMap->ExceptionStubHeaderSize
);
AsmVectorNumFixup ((VOID *) mReservedVectors[Index].HookAfterStubHeaderCode, (UINT8) Index, TRUE);
//
// Go on the following code
//
case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
//
// Save original IDT handler address
//
mReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);
//
// Go on the following code
//
default:
//
// Update new IDT entry
//
InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;
ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
break;
}
}
//
// Save Interrupt number to global variable used for RegisterCpuInterruptHandler ()
//
mEnabledInterruptNum = IdtEntryCount;
}
/**
Internal worker function to initialize exception handler.
@param[in] VectorInfo Pointer to reserved vector list.
@retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
with default exception handlers.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
@retval EFI_UNSUPPORTED This function is not supported.
**/
EFI_STATUS
InitializeCpuExceptionHandlersWorker (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
EFI_STATUS Status;
IA32_DESCRIPTOR IdtDescriptor;
UINTN IdtEntryCount;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
IA32_IDT_GATE_DESCRIPTOR *IdtTable;
mReservedVectors = mReservedVectorsData;
SetMem((VOID *) mReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, mReservedVectors, CPU_EXCEPTION_NUM);
if (EFI_ERROR(Status)) {
return EFI_INVALID_PARAMETER;
}
}
InitializeSpinLock (&mDisplayMessageSpinLock);
mExternalInterruptHandler = mExternalInterruptHandlerTable;
//
// Read IDT descriptor and calculate IDT size
//
AsmReadIdtr (&IdtDescriptor);
IdtEntryCount = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
if (IdtEntryCount > CPU_EXCEPTION_NUM) {
//
// CPU exeption library only setup CPU_EXCEPTION_NUM exception handler at most
//
IdtEntryCount = CPU_EXCEPTION_NUM;
}
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
AsmGetTemplateAddressMap (&TemplateMap);
ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
UpdateIdtTable (IdtTable, &TemplateMap, IdtEntryCount);
mEnabledInterruptNum = IdtEntryCount;
return EFI_SUCCESS;
}
/**
Registers a function to be called from the processor interrupt handler.
@param[in] InterruptType Defines which interrupt or exception to hook.
@param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
when a processor interrupt occurs. If this parameter is NULL, then the handler
will be uninstalled.
@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
previously installed.
@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
previously installed.
@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
or this function is not supported.
**/
EFI_STATUS
RegisterCpuInterruptHandlerWorker (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)mEnabledInterruptNum ||
mReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) {
return EFI_UNSUPPORTED;
}
if (InterruptHandler == NULL && mExternalInterruptHandler[InterruptType] == NULL) {
return EFI_INVALID_PARAMETER;
}
if (InterruptHandler != NULL && mExternalInterruptHandler[InterruptType] != NULL) {
return EFI_ALREADY_STARTED;
}
mExternalInterruptHandler[InterruptType] = InterruptHandler;
return EFI_SUCCESS;
}

202
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
View File

@ -1,202 +0,0 @@
/** @file
IA32 CPU Exception Handler functons.
Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuExceptionCommon.h"
/**
Return address map of exception handler template so that C code can generate
exception tables.
@param IdtEntry Pointer to IDT entry to be updated.
@param InterruptHandler IDT handler value.
**/
VOID
ArchUpdateIdtEntry (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
IN UINTN InterruptHandler
)
{
IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
}
/**
Read IDT handler value from IDT entry.
@param IdtEntry Pointer to IDT entry to be read.
**/
UINTN
ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
)
{
return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16);
}
/**
Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
ArchSaveExceptionContext (
IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
IA32_EFLAGS32 Eflags;
//
// Save Exception context in global variable
//
mReservedVectors[ExceptionType].OldFlags = SystemContext.SystemContextIa32->Eflags;
mReservedVectors[ExceptionType].OldCs = SystemContext.SystemContextIa32->Cs;
mReservedVectors[ExceptionType].OldIp = SystemContext.SystemContextIa32->Eip;
mReservedVectors[ExceptionType].ExceptionData = SystemContext.SystemContextIa32->ExceptionData;
//
// Clear IF flag to avoid old IDT handler enable interrupt by IRET
//
Eflags.UintN = SystemContext.SystemContextIa32->Eflags;
Eflags.Bits.IF = 0;
SystemContext.SystemContextIa32->Eflags = Eflags.UintN;
//
// Modify the EIP in stack, then old IDT handler will return to the stub code
//
SystemContext.SystemContextIa32->Eip = (UINTN) mReservedVectors[ExceptionType].HookAfterStubHeaderCode;
}
/**
Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
ArchRestoreExceptionContext (
IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
SystemContext.SystemContextIa32->Eflags = mReservedVectors[ExceptionType].OldFlags;
SystemContext.SystemContextIa32->Cs = mReservedVectors[ExceptionType].OldCs;
SystemContext.SystemContextIa32->Eip = mReservedVectors[ExceptionType].OldIp;
SystemContext.SystemContextIa32->ExceptionData = mReservedVectors[ExceptionType].ExceptionData;
}
/**
Display CPU information.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
DumpCpuContent (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINTN ImageBase;
UINTN EntryPoint;
InternalPrintMessage (
"!!!! IA32 Exception Type - %08x CPU Apic ID - %08x !!!!\n",
ExceptionType,
GetApicId ()
);
InternalPrintMessage (
"EIP - %08x, CS - %08x, EFLAGS - %08x\n",
SystemContext.SystemContextIa32->Eip,
SystemContext.SystemContextIa32->Cs,
SystemContext.SystemContextIa32->Eflags
);
if ((mErrorCodeFlag & (1 << ExceptionType)) != 0) {
InternalPrintMessage (
"ExceptionData - %08x\n",
SystemContext.SystemContextIa32->ExceptionData
);
}
InternalPrintMessage (
"EAX - %08x, ECX - %08x, EDX - %08x, EBX - %08x\n",
SystemContext.SystemContextIa32->Eax,
SystemContext.SystemContextIa32->Ecx,
SystemContext.SystemContextIa32->Edx,
SystemContext.SystemContextIa32->Ebx
);
InternalPrintMessage (
"ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
SystemContext.SystemContextIa32->Esp,
SystemContext.SystemContextIa32->Ebp,
SystemContext.SystemContextIa32->Esi,
SystemContext.SystemContextIa32->Edi
);
InternalPrintMessage (
"DS - %08x, ES - %08x, FS - %08x, GS - %08x, SS - %08x\n",
SystemContext.SystemContextIa32->Ds,
SystemContext.SystemContextIa32->Es,
SystemContext.SystemContextIa32->Fs,
SystemContext.SystemContextIa32->Gs,
SystemContext.SystemContextIa32->Ss
);
InternalPrintMessage (
"CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
SystemContext.SystemContextIa32->Cr0,
SystemContext.SystemContextIa32->Cr2,
SystemContext.SystemContextIa32->Cr3,
SystemContext.SystemContextIa32->Cr4
);
InternalPrintMessage (
"DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
SystemContext.SystemContextIa32->Dr0,
SystemContext.SystemContextIa32->Dr1,
SystemContext.SystemContextIa32->Dr2,
SystemContext.SystemContextIa32->Dr3
);
InternalPrintMessage (
"DR6 - %08x, DR7 - %08x\n",
SystemContext.SystemContextIa32->Dr6,
SystemContext.SystemContextIa32->Dr7
);
InternalPrintMessage (
"GDTR - %08x %08x, IDTR - %08x %08x\n",
SystemContext.SystemContextIa32->Gdtr[0],
SystemContext.SystemContextIa32->Gdtr[1],
SystemContext.SystemContextIa32->Idtr[0],
SystemContext.SystemContextIa32->Idtr[1]
);
InternalPrintMessage (
"LDTR - %08x, TR - %08x\n",
SystemContext.SystemContextIa32->Ldtr,
SystemContext.SystemContextIa32->Tr
);
InternalPrintMessage (
"FXSAVE_STATE - %08x\n",
&SystemContext.SystemContextIa32->FxSaveState
);
//
// Find module image base and module entry point by RIP
//
ImageBase = FindModuleImageBase (SystemContext.SystemContextIa32->Eip, &EntryPoint);
if (ImageBase != 0) {
InternalPrintMessage (
" (ImageBase=%08x, EntryPoint=%08x) !!!!\n",
ImageBase,
EntryPoint
);
}
}

642
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S
View File

@ -1,642 +0,0 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#* ExceptionHandlerAsm.S
#*
#* Abstract:
#*
#* IA32 CPU Exception Handler
#
#------------------------------------------------------------------------------
#.MMX
#.XMM
ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
#EXTRN ASM_PFX(mDoFarReturnFlag):DWORD # Do far return flag
.text
#
# exception handler stub table
#
Exception0Handle:
.byte 0x6a # push #VectorNum
.byte 0
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception1Handle:
.byte 0x6a # push #VectorNum
.byte 1
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception2Handle:
.byte 0x6a # push #VectorNum
.byte 2
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception3Handle:
.byte 0x6a # push #VectorNum
.byte 3
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception4Handle:
.byte 0x6a # push #VectorNum
.byte 4
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception5Handle:
.byte 0x6a # push #VectorNum
.byte 5
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception6Handle:
.byte 0x6a # push #VectorNum
.byte 6
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception7Handle:
.byte 0x6a # push #VectorNum
.byte 7
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception8Handle:
.byte 0x6a # push #VectorNum
.byte 8
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception9Handle:
.byte 0x6a # push #VectorNum
.byte 9
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception10Handle:
.byte 0x6a # push #VectorNum
.byte 10
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception11Handle:
.byte 0x6a # push #VectorNum
.byte 11
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception12Handle:
.byte 0x6a # push #VectorNum
.byte 12
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception13Handle:
.byte 0x6a # push #VectorNum
.byte 13
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception14Handle:
.byte 0x6a # push #VectorNum
.byte 14
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception15Handle:
.byte 0x6a # push #VectorNum
.byte 15
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception16Handle:
.byte 0x6a # push #VectorNum
.byte 16
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception17Handle:
.byte 0x6a # push #VectorNum
.byte 17
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception18Handle:
.byte 0x6a # push #VectorNum
.byte 18
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception19Handle:
.byte 0x6a # push #VectorNum
.byte 19
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception20Handle:
.byte 0x6a # push #VectorNum
.byte 20
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception21Handle:
.byte 0x6a # push #VectorNum
.byte 21
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception22Handle:
.byte 0x6a # push #VectorNum
.byte 22
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception23Handle:
.byte 0x6a # push #VectorNum
.byte 23
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception24Handle:
.byte 0x6a # push #VectorNum
.byte 24
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception25Handle:
.byte 0x6a # push #VectorNum
.byte 25
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception26Handle:
.byte 0x6a # push #VectorNum
.byte 26
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception27Handle:
.byte 0x6a # push #VectorNum
.byte 27
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception28Handle:
.byte 0x6a # push #VectorNum
.byte 28
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception29Handle:
.byte 0x6a # push #VectorNum
.byte 29
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception30Handle:
.byte 0x6a # push #VectorNum
.byte 30
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
Exception31Handle:
.byte 0x6a # push #VectorNum
.byte 31
pushl %eax
.byte 0xB8
.long ASM_PFX(CommonInterruptEntry)
jmp *%eax
HookAfterStubBegin:
.byte 0x6a # push
VectorNum:
.byte 0 # 0 will be fixed
pushl %eax
.byte 0xB8 # movl ASM_PFX(HookAfterStubHeaderEnd), %eax
.long ASM_PFX(HookAfterStubHeaderEnd)
jmp *%eax
ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
ASM_PFX(HookAfterStubHeaderEnd):
popl %eax
subl $8, %esp # reserve room for filling exception data later
pushl 8(%esp)
xchgl (%esp), %ecx # get vector number
bt %ecx, ASM_PFX(mErrorCodeFlag)
jnc NoErrorData
pushl (%esp) # addition push if exception data needed
NoErrorData:
xchg (%esp), %ecx # restore ecx
pushl %eax
#---------------------------------------;
# CommonInterruptEntry ;
#---------------------------------------;
# The follow algorithm is used for the common interrupt routine.
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_PFX(CommonInterruptEntry):
cli
popl %eax
#
# All interrupt handlers are invoked through interrupt gates, so
# IF flag automatically cleared at the entry point
#
#
# Get vector number from top of stack
#
xchgl (%esp), %ecx
andl $0x0FF, %ecx # Vector number should be less than 256
cmpl $32, %ecx # Intel reserved vector for exceptions?
jae NoErrorCode
bt %ecx, ASM_PFX(mErrorCodeFlag)
jc HasErrorCode
NoErrorCode:
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + ECX +
# +---------------------+ <-- ESP
#
# Registers:
# ECX - Vector Number
#
#
# Put Vector Number on stack
#
pushl %ecx
#
# Put 0 (dummy) error code on stack, and restore ECX
#
xorl %ecx, %ecx # ECX = 0
xchgl 4(%esp), %ecx
jmp ErrorCodeAndVectorOnStack
HasErrorCode:
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + ECX +
# +---------------------+ <-- ESP
#
# Registers:
# ECX - Vector Number
#
#
# Put Vector Number on stack and restore ECX
#
xchgl (%esp), %ecx
ErrorCodeAndVectorOnStack:
pushl %ebp
movl %esp, %ebp
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + Vector Number +
# +---------------------+
# + EBP +
# +---------------------+ <-- EBP
#
#
# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
# is 16-byte aligned
#
andl $0x0fffffff0, %esp
subl $12, %esp
subl $8, %esp
pushl $0 # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
pushl $0 # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
pushl %eax
pushl %ecx
pushl %edx
pushl %ebx
leal 24(%ebp), %ecx
pushl %ecx # ESP
pushl (%ebp) # EBP
pushl %esi
pushl %edi
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
movl %ss, %eax
pushl %eax
movzwl 16(%ebp), %eax
pushl %eax
movl %ds, %eax
pushl %eax
movl %es, %eax
pushl %eax
movl %fs, %eax
pushl %eax
movl %gs, %eax
pushl %eax
#; UINT32 Eip;
movl 12(%ebp), %eax
pushl %eax
#; UINT32 Gdtr[2], Idtr[2];
subl $8, %esp
sidt (%esp)
movl 2(%esp), %eax
xchgl (%esp), %eax
andl $0x0FFFF, %eax
movl %eax, 4(%esp)
subl $8, %esp
sgdt (%esp)
movl 2(%esp), %eax
xchgl (%esp), %eax
andl $0x0FFFF, %eax
movl %eax, 4(%esp)
#; UINT32 Ldtr, Tr;
xorl %eax, %eax
str %ax
pushl %eax
sldt %ax
pushl %eax
#; UINT32 EFlags;
movl 20(%ebp), %eax
pushl %eax
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
movl %cr4, %eax
orl $0x208, %eax
movl %eax, %cr4
pushl %eax
movl %cr3, %eax
pushl %eax
movl %cr2, %eax
pushl %eax
xorl %eax, %eax
pushl %eax
movl %cr0, %eax
pushl %eax
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
movl %dr7, %eax
pushl %eax
movl %dr6, %eax
pushl %eax
movl %dr3, %eax
pushl %eax
movl %dr2, %eax
pushl %eax
movl %dr1, %eax
pushl %eax
movl %dr0, %eax
pushl %eax
#; FX_SAVE_STATE_IA32 FxSaveState;
subl $512, %esp
movl %esp, %edi
.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld
#; UINT32 ExceptionData;
pushl 8(%ebp)
#; Prepare parameter and call
movl %esp, %edx
pushl %edx
movl 4(%ebp), %edx
pushl %edx
#
# Call External Exception Handler
#
call ASM_PFX(CommonExceptionHandler)
addl $8, %esp
cli
#; UINT32 ExceptionData;
addl $4, %esp
#; FX_SAVE_STATE_IA32 FxSaveState;
movl %esp, %esi
.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
addl $512, %esp
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
#; Skip restoration of DRx registers to support in-circuit emualators
#; or debuggers set breakpoint in interrupt/exception context
addl $24, %esp
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
popl %eax
movl %eax, %cr0
addl $4, %esp # not for Cr1
popl %eax
movl %eax, %cr2
popl %eax
movl %eax, %cr3
popl %eax
movl %eax, %cr4
#; UINT32 EFlags;
popl 20(%ebp)
#; UINT32 Ldtr, Tr;
#; UINT32 Gdtr[2], Idtr[2];
#; Best not let anyone mess with these particular registers...
addl $24, %esp
#; UINT32 Eip;
popl 12(%ebp)
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
#; NOTE - modified segment registers could hang the debugger... We
#; could attempt to insulate ourselves against this possibility,
#; but that poses risks as well.
#;
popl %gs
popl %fs
popl %es
popl %ds
popl 16(%ebp)
popl %ss
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
popl %edi
popl %esi
addl $4, %esp # not for ebp
addl $4, %esp # not for esp
popl %ebx
popl %edx
popl %ecx
popl %eax
popl -8(%ebp)
popl -4(%ebp)
movl %ebp, %esp
popl %ebp
addl $8, %esp
cmpl $0, -16(%esp) # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
jz DoReturn
cmpl $1, -20(%esp) # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
jz ErrorCode
jmp *-16(%esp)
ErrorCode:
subl $4, %esp
jmp *-12(%esp)
DoReturn:
cmpl $0, ASM_PFX(mDoFarReturnFlag)
jz DoIret
pushl 8(%esp) # save EFLAGS
addl $16, %esp
pushl -8(%esp) # save CS in new location
pushl -8(%esp) # save EIP in new location
pushl -8(%esp) # save EFLAGS in new location
popfl # restore EFLAGS
retf # far return
DoIret:
iretl
#---------------------------------------;
# _AsmGetTemplateAddressMap ;
#---------------------------------------;
#
# Protocol prototype
# AsmGetTemplateAddressMap (
# EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
# );
#
# Routine Description:
#
# Return address map of interrupt handler template so that C code can generate
# interrupt table.
#
# Arguments:
#
#
# Returns:
#
# Nothing
#
#
# Input: [ebp][0] = Original ebp
# [ebp][4] = Return address
#
# Output: Nothing
#
# Destroys: Nothing
#-----------------------------------------------------------------------------;
#-------------------------------------------------------------------------------------
# AsmGetAddressMap (&AddressMap);
#-------------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmGetTemplateAddressMap)
ASM_PFX(AsmGetTemplateAddressMap):
pushl %ebp
movl %esp,%ebp
pushal
movl 0x8(%ebp), %ebx
movl $Exception0Handle, (%ebx)
movl $(Exception1Handle - Exception0Handle), 0x4(%ebx)
movl $(HookAfterStubBegin), 0x8(%ebx)
popal
popl %ebp
ret
#-------------------------------------------------------------------------------------
# AsmVectorNumFixup (*VectorBase, VectorNum, HookStub);
#-------------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmVectorNumFixup)
ASM_PFX(AsmVectorNumFixup):
movl 8(%esp), %eax
movl 4(%esp), %ecx
movb %al, (VectorNum - HookAfterStubBegin)(%ecx)
ret

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CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.uni
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CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.uni
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CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
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/** @file
x64 CPU Exception Handler.
Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuExceptionCommon.h"
/**
Return address map of exception handler template so that C code can generate
exception tables.
@param IdtEntry Pointer to IDT entry to be updated.
@param InterruptHandler IDT handler value.
**/
VOID
ArchUpdateIdtEntry (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
IN UINTN InterruptHandler
)
{
IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
IdtEntry->Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
}
/**
Read IDT handler value from IDT entry.
@param IdtEntry Pointer to IDT entry to be read.
**/
UINTN
ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
)
{
return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh) << 16) +
(((UINTN) IdtEntry->Bits.OffsetUpper) << 32);
}
/**
Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
ArchSaveExceptionContext (
IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
IA32_EFLAGS32 Eflags;
//
// Save Exception context in global variable
//
mReservedVectors[ExceptionType].OldSs = SystemContext.SystemContextX64->Ss;
mReservedVectors[ExceptionType].OldSp = SystemContext.SystemContextX64->Rsp;
mReservedVectors[ExceptionType].OldFlags = SystemContext.SystemContextX64->Rflags;
mReservedVectors[ExceptionType].OldCs = SystemContext.SystemContextX64->Cs;
mReservedVectors[ExceptionType].OldIp = SystemContext.SystemContextX64->Rip;
mReservedVectors[ExceptionType].ExceptionData = SystemContext.SystemContextX64->ExceptionData;
//
// Clear IF flag to avoid old IDT handler enable interrupt by IRET
//
Eflags.UintN = SystemContext.SystemContextX64->Rflags;
Eflags.Bits.IF = 0;
SystemContext.SystemContextX64->Rflags = Eflags.UintN;
//
// Modify the EIP in stack, then old IDT handler will return to the stub code
//
SystemContext.SystemContextX64->Rip = (UINTN) mReservedVectors[ExceptionType].HookAfterStubHeaderCode;
}
/**
Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
ArchRestoreExceptionContext (
IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
SystemContext.SystemContextX64->Ss = mReservedVectors[ExceptionType].OldSs;
SystemContext.SystemContextX64->Rsp = mReservedVectors[ExceptionType].OldSp;
SystemContext.SystemContextX64->Rflags = mReservedVectors[ExceptionType].OldFlags;
SystemContext.SystemContextX64->Cs = mReservedVectors[ExceptionType].OldCs;
SystemContext.SystemContextX64->Rip = mReservedVectors[ExceptionType].OldIp;
SystemContext.SystemContextX64->ExceptionData = mReservedVectors[ExceptionType].ExceptionData;
}
/**
Display CPU information.
@param ExceptionType Exception type.
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
DumpCpuContent (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINTN ImageBase;
UINTN EntryPoint;
InternalPrintMessage (
"!!!! X64 Exception Type - %016lx CPU Apic ID - %08x !!!!\n",
ExceptionType,
GetApicId ()
);
InternalPrintMessage (
"RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n",
SystemContext.SystemContextX64->Rip,
SystemContext.SystemContextX64->Cs,
SystemContext.SystemContextX64->Rflags
);
if (mErrorCodeFlag & (1 << ExceptionType)) {
InternalPrintMessage (
"ExceptionData - %016lx\n",
SystemContext.SystemContextX64->ExceptionData
);
}
InternalPrintMessage (
"RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
SystemContext.SystemContextX64->Rax,
SystemContext.SystemContextX64->Rcx,
SystemContext.SystemContextX64->Rdx
);
InternalPrintMessage (
"RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
SystemContext.SystemContextX64->Rbx,
SystemContext.SystemContextX64->Rsp,
SystemContext.SystemContextX64->Rbp
);
InternalPrintMessage (
"RSI - %016lx, RDI - %016lx\n",
SystemContext.SystemContextX64->Rsi,
SystemContext.SystemContextX64->Rdi
);
InternalPrintMessage (
"R8 - %016lx, R9 - %016lx, R10 - %016lx\n",
SystemContext.SystemContextX64->R8,
SystemContext.SystemContextX64->R9,
SystemContext.SystemContextX64->R10
);
InternalPrintMessage (
"R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
SystemContext.SystemContextX64->R11,
SystemContext.SystemContextX64->R12,
SystemContext.SystemContextX64->R13
);
InternalPrintMessage (
"R14 - %016lx, R15 - %016lx\n",
SystemContext.SystemContextX64->R14,
SystemContext.SystemContextX64->R15
);
InternalPrintMessage (
"DS - %016lx, ES - %016lx, FS - %016lx\n",
SystemContext.SystemContextX64->Ds,
SystemContext.SystemContextX64->Es,
SystemContext.SystemContextX64->Fs
);
InternalPrintMessage (
"GS - %016lx, SS - %016lx\n",
SystemContext.SystemContextX64->Gs,
SystemContext.SystemContextX64->Ss
);
InternalPrintMessage (
"CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
SystemContext.SystemContextX64->Cr0,
SystemContext.SystemContextX64->Cr2,
SystemContext.SystemContextX64->Cr3
);
InternalPrintMessage (
"CR4 - %016lx, CR8 - %016lx\n",
SystemContext.SystemContextX64->Cr4,
SystemContext.SystemContextX64->Cr8
);
InternalPrintMessage (
"DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
SystemContext.SystemContextX64->Dr0,
SystemContext.SystemContextX64->Dr1,
SystemContext.SystemContextX64->Dr2
);
InternalPrintMessage (
"DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
SystemContext.SystemContextX64->Dr3,
SystemContext.SystemContextX64->Dr6,
SystemContext.SystemContextX64->Dr7
);
InternalPrintMessage (
"GDTR - %016lx %016lx, LDTR - %016lx\n",
SystemContext.SystemContextX64->Gdtr[0],
SystemContext.SystemContextX64->Gdtr[1],
SystemContext.SystemContextX64->Ldtr
);
InternalPrintMessage (
"IDTR - %016lx %016lx, TR - %016lx\n",
SystemContext.SystemContextX64->Idtr[0],
SystemContext.SystemContextX64->Idtr[1],
SystemContext.SystemContextX64->Tr
);
InternalPrintMessage (
"FXSAVE_STATE - %016lx\n",
&SystemContext.SystemContextX64->FxSaveState
);
//
// Find module image base and module entry point by RIP
//
ImageBase = FindModuleImageBase (SystemContext.SystemContextX64->Rip, &EntryPoint);
if (ImageBase != 0) {
InternalPrintMessage (
" (ImageBase=%016lx, EntryPoint=%016lx) !!!!\n",
ImageBase,
EntryPoint
);
}
}

641
CloverEFI/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.S
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@ -1,641 +0,0 @@
#------------------------------------------------------------------------------ ;
# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# ExceptionHandlerAsm.S
#
# Abstract:
#
# x64 CPU Exception Handler
#
# Notes:
#
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
#ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
#ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
#EXTRN ASM_PFX(mDoFarReturnFlag):QWORD # Do far return flag
.text
.align 3
#
# exception handler stub table
#
Exception0Handle:
.byte 0x6a # push #VectorNum
.byte 0
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception1Handle:
.byte 0x6a # push #VectorNum
.byte 1
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception2Handle:
.byte 0x6a # push #VectorNum
.byte 2
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception3Handle:
.byte 0x6a # push #VectorNum
.byte 3
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception4Handle:
.byte 0x6a # push #VectorNum
.byte 4
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception5Handle:
.byte 0x6a # push #VectorNum
.byte 5
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception6Handle:
.byte 0x6a # push #VectorNum
.byte 6
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception7Handle:
.byte 0x6a # push #VectorNum
.byte 7
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception8Handle:
.byte 0x6a # push #VectorNum
.byte 8
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception9Handle:
.byte 0x6a # push #VectorNum
.byte 9
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception10Handle:
.byte 0x6a # push #VectorNum
.byte 10
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception11Handle:
.byte 0x6a # push #VectorNum
.byte 11
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception12Handle:
.byte 0x6a # push #VectorNum
.byte 12
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception13Handle:
.byte 0x6a # push #VectorNum
.byte 13
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception14Handle:
.byte 0x6a # push #VectorNum
.byte 14
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception15Handle:
.byte 0x6a # push #VectorNum
.byte 15
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception16Handle:
.byte 0x6a # push #VectorNum
.byte 16
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception17Handle:
.byte 0x6a # push #VectorNum
.byte 17
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception18Handle:
.byte 0x6a # push #VectorNum
.byte 18
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception19Handle:
.byte 0x6a # push #VectorNum
.byte 19
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception20Handle:
.byte 0x6a # push #VectorNum
.byte 20
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception21Handle:
.byte 0x6a # push #VectorNum
.byte 21
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception22Handle:
.byte 0x6a # push #VectorNum
.byte 22
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception23Handle:
.byte 0x6a # push #VectorNum
.byte 23
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception24Handle:
.byte 0x6a # push #VectorNum
.byte 24
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception25Handle:
.byte 0x6a # push #VectorNum
.byte 25
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception26Handle:
.byte 0x6a # push #VectorNum
.byte 26
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception27Handle:
.byte 0x6a # push #VectorNum
.byte 27
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception28Handle:
.byte 0x6a # push #VectorNum
.byte 28
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception29Handle:
.byte 0x6a # push #VectorNum
.byte 29
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception30Handle:
.byte 0x6a # push #VectorNum
.byte 30
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
Exception31Handle:
.byte 0x6a # push #VectorNum
.byte 31
pushq %rax
.byte 0x48, 0xB8
.quad 0 #ASM_PFX(CommonInterruptEntry)
jmp *%rax
HookAfterStubHeaderBegin:
.byte 0x6a # push
#VectorNum:
PatchVectorNum:
.byte 0 # 0 will be fixed
pushq %rax
.byte 0x48, 0xB8 # movq ASM_PFX(HookAfterStubHeaderEnd), %rax
# .quad ASM_PFX(HookAfterStubHeaderEnd)
PatchFuncAddress:
.quad 0
jmp *%rax
ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
ASM_PFX(HookAfterStubHeaderEnd):
movq %rsp, %rax
andl $0x0fffffff0, %esp # make sure 16-byte aligned for exception context
subq $0x18, %rsp # reserve room for filling exception data later
pushq %rcx
movq 8(%rax), %rcx
# pushq %rax
# movabsl ASM_PFX(mErrorCodeFlag), %eax
# bt %ecx, %eax
# popq %rax
bt %ecx, ASM_PFX(mErrorCodeFlag)(%rip)
jnc NoErrorData
pushq (%rsp) # push additional rcx to make stack alignment
NoErrorData:
xchgq (%rsp), %rcx # restore rcx, save Exception Number in stack
pushq (%rax) # push rax into stack to keep code consistence
#---------------------------------------;
# CommonInterruptEntry ;
#---------------------------------------;
# The follow algorithm is used for the common interrupt routine.
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_PFX(CommonInterruptEntry):
cli
popq %rax
#
# All interrupt handlers are invoked through interrupt gates, so
# IF flag automatically cleared at the entry point
#
#
# Calculate vector number
#
xchgq (%rsp), %rcx # get the return address of call, actually, it is the address of vector number.
andq $0x0FF, %rcx
cmp $32, %ecx # Intel reserved vector for exceptions?
jae NoErrorCode
pushq %rax
# movabsl ASM_PFX(mErrorCodeFlag), %eax
movl ASM_PFX(mErrorCodeFlag)(%rip), %eax
bt %ecx, %eax
popq %rax
jc CommonInterruptEntry_al_0000
NoErrorCode:
#
# Push a dummy error code on the stack
# to maintain coherent stack map
#
pushq (%rsp)
movq $0, 8(%rsp)
CommonInterruptEntry_al_0000:
pushq %rbp
movq %rsp, %rbp
pushq $0 # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
pushq $0 # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
#
# Stack:
# +---------------------+ <-- 16-byte aligned ensured by processor
# + Old SS +
# +---------------------+
# + Old RSP +
# +---------------------+
# + RFlags +
# +---------------------+
# + CS +
# +---------------------+
# + RIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + RCX / Vector Number +
# +---------------------+
# + RBP +
# +---------------------+ <-- RBP, 16-byte aligned
#
#
# Since here the stack pointer is 16-byte aligned, so
# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
# is 16-byte aligned
#
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %r11
pushq %r10
pushq %r9
pushq %r8
pushq %rax
pushq 8(%rbp) # RCX
pushq %rdx
pushq %rbx
pushq 48(%rbp) # RSP
pushq (%rbp) # RBP
pushq %rsi
pushq %rdi
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
movzwq 56(%rbp), %rax
pushq %rax # for ss
movzwq 32(%rbp), %rax
pushq %rax # for cs
movl %ds, %eax
pushq %rax
movl %es, %eax
pushq %rax
movl %fs, %eax
pushq %rax
movl %gs, %eax
pushq %rax
movq %rcx, 8(%rbp) # save vector number
#; UINT64 Rip;
pushq 24(%rbp)
#; UINT64 Gdtr[2], Idtr[2];
xorq %rax, %rax
pushq %rax
pushq %rax
sidt (%rsp)
xchgq 2(%rsp), %rax
xchgq (%rsp), %rax
xchgq 8(%rsp), %rax
xorq %rax, %rax
pushq %rax
pushq %rax
sgdt (%rsp)
xchgq 2(%rsp), %rax
xchgq (%rsp), %rax
xchgq 8(%rsp), %rax
#; UINT64 Ldtr, Tr;
xorq %rax, %rax
str %ax
pushq %rax
sldt %ax
pushq %rax
#; UINT64 RFlags;
pushq 40(%rbp)
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
movq %cr8, %rax
pushq %rax
movq %cr4, %rax
orq $0x208, %rax
movq %rax, %cr4
pushq %rax
mov %cr3, %rax
pushq %rax
mov %cr2, %rax
pushq %rax
xorq %rax, %rax
pushq %rax
mov %cr0, %rax
pushq %rax
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
movq %dr7, %rax
pushq %rax
movq %dr6, %rax
pushq %rax
movq %dr3, %rax
pushq %rax
movq %dr2, %rax
pushq %rax
movq %dr1, %rax
pushq %rax
movq %dr0, %rax
pushq %rax
#; FX_SAVE_STATE_X64 FxSaveState;
subq $512, %rsp
movq %rsp, %rdi
.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
#; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld
#; UINT32 ExceptionData;
pushq 16(%rbp)
#; Prepare parameter and call
mov 8(%rbp), %rcx
mov %rsp, %rdx
#
# Per X64 calling convention, allocate maximum parameter stack space
# and make sure RSP is 16-byte aligned
#
subq $40, %rsp
call ASM_PFX(CommonExceptionHandler)
addq $40, %rsp
cli
#; UINT64 ExceptionData;
addq $8, %rsp
#; FX_SAVE_STATE_X64 FxSaveState;
movq %rsp, %rsi
.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
addq $512, %rsp
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
#; Skip restoration of DRx registers to support in-circuit emualators
#; or debuggers set breakpoint in interrupt/exception context
addq $48, %rsp
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
popq %rax
movq %rax, %cr0
addq $8, %rsp # not for Cr1
popq %rax
movq %rax, %cr2
popq %rax
movq %rax, %cr3
popq %rax
movq %rax, %cr4
popq %rax
movq %rax, %cr8
#; UINT64 RFlags;
popq 40(%rbp)
#; UINT64 Ldtr, Tr;
#; UINT64 Gdtr[2], Idtr[2];
#; Best not let anyone mess with these particular registers...
addq $48, %rsp
#; UINT64 Rip;
popq 24(%rbp)
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
popq %rax
# mov %rax, %gs ; not for gs
popq %rax
# mov %rax, %fs ; not for fs
# (X64 will not use fs and gs, so we do not restore it)
popq %rax
movl %eax, %es
popq %rax
movl %eax, %ds
popq 32(%rbp) # for cs
popq 56(%rbp) # for ss
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
popq %rdi
popq %rsi
addq $8, %rsp # not for rbp
popq 48(%rbp) # for rsp
popq %rbx
popq %rdx
popq %rcx
popq %rax
popq %r8
popq %r9
popq %r10
popq %r11
popq %r12
popq %r13
popq %r14
popq %r15
movq %rbp, %rsp
popq %rbp
addq $16, %rsp
cmpq $0, -32(%rsp) # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
jz DoReturn # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
cmpb $1, -40(%rsp)
jz ErrorCode
jmp *-32(%rsp)
ErrorCode:
subq $8, %rsp
jmp *-24(%rsp)
DoReturn:
pushq %rax
# movabsq ASM_PFX(mDoFarReturnFlag), %rax
movq ASM_PFX(mDoFarReturnFlag)(%rip), %rax
cmpq $0, %rax # Check if need to do far return instead of IRET
popq %rax
jz DoIret
pushq %rax
movq %rsp, %rax # save old RSP to rax
movq 0x20(%rsp), %rsp
pushq 0x10(%rax) # save CS in new location
pushq 0x8(%rax) # save EIP in new location
pushq 0x18(%rax) # save EFLAGS in new location
movq (%rax), %rax # restore rax
popfq # restore EFLAGS
# .byte 0x48 # prefix to composite "retq" with next "retf"
# lretq #retf # far return
.byte 0x48 # prefix to composite "retq" with next "retf"
#ifdef __APPLE__
.byte 0xCB
#else
retf # far return
#endif
DoIret:
iretq
#-------------------------------------------------------------------------------------
# AsmGetTemplateAddressMap (&AddressMap);
#-------------------------------------------------------------------------------------
# comments here for definition of address map
ASM_GLOBAL ASM_PFX(AsmGetTemplateAddressMap)
ASM_PFX(AsmGetTemplateAddressMap):
# movabsq $Exception0Handle, %rax
# movq %rax, (%rcx)
# movq $(Exception1Handle - Exception0Handle), 0x08(%rcx)
# movabsq $HookAfterStubHeaderBegin, %rax
# movq %rax, 0x10(%rcx)
# ret
leaq Exception0Handle(%rip), %rax
movq %rax, (%rcx)
movq $(Exception1Handle - Exception0Handle), 0x08(%rcx)
leaq HookAfterStubHeaderBegin(%rip), %rax
movq %rax, 0x10(%rcx)
ret
#-------------------------------------------------------------------------------------
# VOID
# EFIAPI
# AsmVectorNumFixup (
# IN VOID *VectorBase, // RCX
# IN UINT8 VectorNum, // RDX
# IN BOOLEAN HookStub // R8
# );
#-------------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmVectorNumFixup)
ASM_PFX(AsmVectorNumFixup):
# movq %rdx, %rax
# movb %al, (VectorNum - HookAfterStubHeaderBegin)(%rcx)
# ret
pushq %rbp
movq %rsp, %rbp
# Patch vector #
movb %dl, (PatchVectorNum - HookAfterStubHeaderBegin)(%rcx)
# Patch Function address
leaq ASM_PFX(HookAfterStubHeaderEnd)(%rip), %rax
leaq ASM_PFX(CommonInterruptEntry)(%rip), %r10
testb %r8b, %r8b
cmovneq %rax, %r10
movq %r10, (PatchFuncAddress - HookAfterStubHeaderBegin)(%rcx)
popq %rbp
ret
#END

1692
CloverEFI/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
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File diff suppressed because it is too large Load Diff

41
CloverEFI/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
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@ -1,41 +0,0 @@
## @file
# MTRR library provides API for MTRR operation
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = MtrrLib
FILE_GUID = 6826b408-f4f3-47ee-917f-af7047f9d937
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = MtrrLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
MtrrLib.c
[Packages]
MdePkg/MdePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseMemoryLib
BaseLib
CpuLib

216
CloverEFI/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/IpfTimerLib.c
View File

@ -1,216 +0,0 @@
/** @file
Timer Library functions built upon ITC on IPF.
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/PalLib.h>
/**
Performs a delay measured as number of ticks.
An internal function to perform a delay measured as number of ticks. It's
invoked by MicroSecondDelay() and NanoSecondDelay().
@param Delay The number of ticks to delay.
**/
VOID
EFIAPI
InternalIpfDelay (
IN INT64 Delay
)
{
INT64 Ticks;
//
// The target timer count is calculated here
//
Ticks = (INT64)AsmReadItc () + Delay;
//
// Wait until time out
// Delay > 2^63 could not be handled by this function
// Timer wrap-arounds are handled correctly by this function
//
while (Ticks - (INT64)AsmReadItc() >= 0);
}
/**
Stalls the CPU for at least the given number of microseconds.
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@param MicroSeconds The minimum number of microseconds to delay.
@return The value of MicroSeconds inputted.
**/
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
InternalIpfDelay (
GetPerformanceCounterProperties (NULL, NULL) *
MicroSeconds /
1000000
);
return MicroSeconds;
}
/**
Stalls the CPU for at least the given number of nanoseconds.
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
@param NanoSeconds The minimum number of nanoseconds to delay.
@return The value of NanoSeconds inputted.
**/
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
InternalIpfDelay (
GetPerformanceCounterProperties (NULL, NULL) *
NanoSeconds /
1000000000
);
return NanoSeconds;
}
/**
Retrieves the current value of a 64-bit free running performance counter.
The counter can either count up by 1 or count down by 1. If the physical
performance counter counts by a larger increment, then the counter values
must be translated. The properties of the counter can be retrieved from
GetPerformanceCounterProperties().
@return The current value of the free running performance counter.
**/
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return AsmReadItc ();
}
/**
Retrieves the 64-bit frequency in Hz and the range of performance counter
values.
If StartValue is not NULL, then the value that the performance counter starts
with immediately after is it rolls over is returned in StartValue. If
EndValue is not NULL, then the value that the performance counter end with
immediately before it rolls over is returned in EndValue. The 64-bit
frequency of the performance counter in Hz is always returned. If StartValue
is less than EndValue, then the performance counter counts up. If StartValue
is greater than EndValue, then the performance counter counts down. For
example, a 64-bit free running counter that counts up would have a StartValue
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
@param StartValue The value the performance counter starts with when it
rolls over.
@param EndValue The value that the performance counter ends with before
it rolls over.
@return The frequency in Hz.
**/
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
PAL_CALL_RETURN PalRet;
UINT64 BaseFrequence;
if (StartValue != NULL) {
*StartValue = 0;
}
if (EndValue != NULL) {
*EndValue = (UINT64)(-1);
}
PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);
if (PalRet.Status != 0) {
return 1000000;
}
BaseFrequence = PalRet.r9;
PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);
if (PalRet.Status != 0) {
return 1000000;
}
return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;
}
/**
Converts elapsed ticks of performance counter to time in nanoseconds.
This function converts the elapsed ticks of running performance counter to
time value in unit of nanoseconds.
@param Ticks The number of elapsed ticks of running performance counter.
@return The elapsed time in nanoseconds.
**/
UINT64
EFIAPI
GetTimeInNanoSecond (
IN UINT64 Ticks
)
{
UINT64 Frequency;
UINT64 NanoSeconds;
UINT64 Remainder;
INTN Shift;
Frequency = GetPerformanceCounterProperties (NULL, NULL);
//
// Ticks
// Time = --------- x 1,000,000,000
// Frequency
//
NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);
//
// Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33.
//
Shift = MAX (0, HighBitSet64 (Remainder) - 33);
Remainder = RShiftU64 (Remainder, (UINTN) Shift);
Frequency = RShiftU64 (Frequency, (UINTN) Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds;
}

63
CloverEFI/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
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@ -1,63 +0,0 @@
## @file
# Instance of Timer Library only using CPU resources.
#
# Timer Library that only uses CPU resources to provide calibrated delays
# on IA-32, x64, and IPF.
# Note: Because CPU Local APIC and ITC could be programmed by OS, it cannot be
# used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM
# drivers and runtime drivers.
#
# This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in
# that it uses the local APIC library so that it supports x2APIC mode.
#
# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SecPeiDxeTimerLibUefiCpu
FILE_GUID = 4FFF2014-2086-4ee6-9B58-886D1967861C
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib|BASE DXE_CORE DXE_DRIVER DXE_SAL_DRIVER PEIM PEI_CORE SEC UEFI_APPLICATION UEFI_DRIVER
#
# VALID_ARCHITECTURES = IA32 X64 IPF
#
[Sources.Ia32, Sources.X64]
X86TimerLib.c
[Sources.IPF]
IpfTimerLib.c
[Packages]
MdePkg/MdePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseLib
[LibraryClasses.IA32, LibraryClasses.X64]
PcdLib
DebugLib
LocalApicLib
[LibraryClasses.IPF]
PalLib
[Pcd.IA32, Pcd.X64]
gEfiMdePkgTokenSpaceGuid.PcdFSBClock ## CONSUMES

BIN
CloverEFI/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
View File

Binary file not shown.

BIN
CloverEFI/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
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Binary file not shown.

26
CloverEFI/UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm
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@ -1,26 +0,0 @@
;------------------------------------------------------------------------------
; @file
; Debug disabled
;
; Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
BITS 16
%macro debugInitialize 0
;
; No initialization is required
;
%endmacro
%macro debugShowPostCode 1
%endmacro

110
CloverEFI/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
View File

@ -1,110 +0,0 @@
## @file
# Apply fixup to VTF binary image for FFS Raw section
#
# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
import sys
filename = sys.argv[1]
if filename.lower().find('ia32') >= 0:
d = open(sys.argv[1], 'rb').read()
c = ((len(d) + 4 + 7) & ~7) - 4
if c > len(d):
c -= len(d)
f = open(sys.argv[1], 'wb')
f.write('\x90' * c)
f.write(d)
f.close()
else:
from struct import pack
PAGE_PRESENT = 0x01
PAGE_READ_WRITE = 0x02
PAGE_USER_SUPERVISOR = 0x04
PAGE_WRITE_THROUGH = 0x08
PAGE_CACHE_DISABLE = 0x010
PAGE_ACCESSED = 0x020
PAGE_DIRTY = 0x040
PAGE_PAT = 0x080
PAGE_GLOBAL = 0x0100
PAGE_2M_MBO = 0x080
PAGE_2M_PAT = 0x01000
def NopAlign4k(s):
c = ((len(s) + 0xfff) & ~0xfff) - len(s)
return ('\x90' * c) + s
def PageDirectoryEntries4GbOf2MbPages(baseAddress):
s = ''
for i in range(0x800):
i = (
baseAddress + long(i << 21) +
PAGE_2M_MBO +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_DIRTY +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
s = ''
for i in range(0x200):
i = (
pdeBase +
(min(i, 3) << 12) +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def PageMapLevel4Table4GbOf2MbPages(pdptBase):
s = ''
for i in range(0x200):
i = (
pdptBase +
(min(i, 0) << 12) +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def First4GbPageEntries(topAddress):
PDE = PageDirectoryEntries4GbOf2MbPages(0L)
pml4tBase = topAddress - 0x1000
pdptBase = pml4tBase - 0x1000
pdeBase = pdptBase - len(PDE)
PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
return PDE + PDPT + PML4T
def AlignAndAddPageTables():
d = open(sys.argv[1], 'rb').read()
code = NopAlign4k(d)
topAddress = 0x100000000 - len(code)
d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
f = open(sys.argv[1], 'wb')
f.write(d)
f.close()
AlignAndAddPageTables()

46
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
View File

@ -1,46 +0,0 @@
## @file UefiCpuPkg.dec
#
# This Package provides UEFI compatible CPU modules and libraries.
#
# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License which accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = UefiCpuPkg
PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
PACKAGE_VERSION = 0.1
[Includes]
Include
[LibraryClasses]
## @libraryclass Defines some routines that are generic for IA32 family CPU
## to be UEFI specification compliant.
##
UefiCpuLib|Include/Library/UefiCpuLib.h
[LibraryClasses.IA32, LibraryClasses.X64]
## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
##
MtrrLib|Include/Library/MtrrLib.h
## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
##
LocalApicLib|Include/Library/LocalApicLib.h
[Guids]
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
[PcdsFixedAtBuild, PcdsPatchableInModule]
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001

89
CloverEFI/UefiCpuPkg/UefiCpuPkg.dsc
View File

@ -1,89 +0,0 @@
## @file
# UefiCpuPkg Package
#
# Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
PLATFORM_NAME = UefiCpu
PLATFORM_GUID = a1b7be22-78b3-4260-9569-8649e8c17d49
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/UefiCpu
SUPPORTED_ARCHITECTURES = IA32|IPF|X64
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
#
# External libraries to build package
#
[LibraryClasses]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MtrrLib|CloverEFI/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
LocalApicLib|CloverEFI/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
[LibraryClasses.common.PEIM]
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
[LibraryClasses.IA32.PEIM, LibraryClasses.X64.PEIM]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
[LibraryClasses.IPF.PEIM]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf
[LibraryClasses.common.DXE_DRIVER]
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
[LibraryClasses.common.DXE_SMM_DRIVER]
SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
#
# Drivers/Libraries within this package
#
[Components]
CloverEFI/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
CloverEFI/UefiCpuPkg/CpuIoPei/CpuIoPei.inf
CloverEFI/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
[Components.IA32, Components.X64]
CloverEFI/UefiCpuPkg/CpuDxe/CpuDxe.inf
CloverEFI/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
CloverEFI/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
CloverEFI/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
CloverEFI/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
CloverEFI/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
CloverEFI/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf

79
CloverEFI/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
View File

@ -1,79 +0,0 @@
## @file
# S3 Resume Module:
# This module works with StandAloneBootScriptExecutor to S3 resume to OS.
# This module will excute the boot script saved during last boot and after that,
# control is passed to OS waking up handler.
#
# Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are
# licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = S3Resume2Pei
FILE_GUID = 89E549B0-7CFE-449d-9BA3-10D8B2312D71
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = PeimS3ResumeEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
S3Resume.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CloverEFI/UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
PeiServicesTablePointerLib
PerformanceLib
HobLib
PeiServicesLib
PeimEntryPoint
TimerLib
BaseLib
DebugLib
PcdLib
IoLib
BaseMemoryLib
MemoryAllocationLib
DebugAgentLib
LocalApicLib
ReportStatusCodeLib
LockBoxLib
PrintLib
[Guids]
gEfiBootScriptExecutorVariableGuid # SOMETIMES_CONSUMED
gEfiBootScriptExecutorContextGuid # SOMETIMES_CONSUMED
gPerformanceProtocolGuid # ALWAYS_CONSUMED L"PerfDataMemAddr"
gEfiAcpiVariableGuid # ALWAYS_CONSUMED Hob: GUID_EXTENSION
gEfiAcpiS3ContextGuid # ALWAYS_CONSUMED
[Ppis]
gEfiPeiReadOnlyVariable2PpiGuid # PPI ALWAYS_CONSUMED
gEfiPeiS3Resume2PpiGuid # PPI ALWAYS_PRODUCED
gPeiSmmAccessPpiGuid # PPI ALWAYS_CONSUMED
gPeiPostScriptTablePpiGuid # PPI ALWAYS_PRODUCED
gEfiEndOfPeiSignalPpiGuid # PPI ALWAYS_PRODUCED
[FeaturePcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport
[Depex]
gEfiPeiReadOnlyVariable2PpiGuid

73
CloverEFI/UefiCpuPkg/build.sh
View File

@ -1,73 +0,0 @@
#!/bin/bash
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
set -e
shopt -s nocasematch
#
# Setup workspace if it is not set
#
if [ -z "$WORKSPACE" ]
then
echo Initializing workspace
if [ ! -e `pwd`/edksetup.sh ]
then
cd ..
fi
# This version is for the tools in the BaseTools project.
# this assumes svn pulls have the same root dir
# export EDK_TOOLS_PATH=`pwd`/../BaseTools
# This version is for the tools source in edk2
export EDK_TOOLS_PATH=`pwd`/BaseTools
echo $EDK_TOOLS_PATH
source edksetup.sh BaseTools
else
echo Building from: $WORKSPACE
fi
#
# Pick a default tool type for a given OS
#
TARGET_TOOLS=MYTOOLS
NETWORK_SUPPORT=
case `uname` in
CYGWIN*) echo Cygwin not fully supported yet. ;;
Darwin*)
Major=$(uname -r | cut -f 1 -d '.')
if [[ $Major == 9 ]]
then
echo UnixPkg requires Snow Leopard or later OS
exit 1
else
TARGET_TOOLS=XCODE32
fi
# NETWORK_SUPPORT="-D NETWORK_SUPPORT"
;;
Linux*) TARGET_TOOLS=ELFGCC ;;
esac
BUILD_ROOT_ARCH=$WORKSPACE/Build/Shell/DEBUG_"$TARGET_TOOLS"/IA32
#
# Build the edk2 UnixPkg
#
echo $PATH
echo `which build`
#build -p $WORKSPACE/UnixPkg/UnixPkg.dsc -a IA32 -t $TARGET_TOOLS $NETWORK_SUPPORT -n 3 $1 $2 $3 $4 $5 $6 $7 $8
build -p $WORKSPACE/CloverEFI/UefiCpuPkg/UefiCpuPkg.dsc -a IA32 -t $TARGET_TOOLS -n 3 $*
exit $?

283
CloverEFI/UefiCpuPkg/edk2.patch-idtgdt
View File

@ -1,283 +0,0 @@
Index: UefiCpuPkg/CpuDxe/CpuDxe.inf
===================================================================
--- UefiCpuPkg/CpuDxe/CpuDxe.inf (revision 9332)
+++ UefiCpuPkg/CpuDxe/CpuDxe.inf (working copy)
@@ -62,6 +62,9 @@
[Protocols]
gEfiCpuArchProtocolGuid
+[Guids]
+ gEfiEventVirtualAddressChangeGuid # ALWAYS_CONSUMED Create Event: EVENT_GROUP_GUID
+
[Depex]
TRUE
Index: UefiCpuPkg/CpuDxe/CpuGdt.c
===================================================================
--- UefiCpuPkg/CpuDxe/CpuGdt.c (revision 9332)
+++ UefiCpuPkg/CpuDxe/CpuGdt.c (working copy)
@@ -67,6 +67,9 @@
#error CPU type not supported for CPU GDT initialization!
#endif
+VOID * Gdt;
+UINT32 GdtSize;
+
//
// Global descriptor table (GDT) Template
//
@@ -161,6 +164,20 @@
},
};
+VOID EFIAPI
+LoadGdt(VOID* Gdt, UINT32 GdtSize)
+{
+ IA32_DESCRIPTOR gdtPtr;
+
+ //
+ // Write GDT register
+ //
+ gdtPtr.Base = (UINT32)(UINTN)Gdt;
+ gdtPtr.Limit = GdtSize - 1;
+
+ AsmWriteGdtr (&gdtPtr);
+}
+
/**
Initialize Global Descriptor Table
@@ -169,27 +186,27 @@
InitGlobalDescriptorTable (
)
{
- GDT_ENTRIES *gdt;
- IA32_DESCRIPTOR gdtPtr;
-
//
// Allocate Runtime Data for the GDT
//
- gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
- ASSERT (gdt != NULL);
- gdt = ALIGN_POINTER (gdt, 8);
+ GdtSize = sizeof (GdtTemplate);
+#if 0
+ Gdt = AllocateRuntimePool (GdtSize + 8);
+ ASSERT (Gdt != NULL);
+ Gdt = ALIGN_POINTER (Gdt, 8);
+#else
+ Gdt = (VOID*)(UINTN)HandyCpuPage;
+#endif
//
// Initialize all GDT entries
//
- CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));
+ CopyMem (Gdt, &GdtTemplate, GdtSize);
//
// Write GDT register
//
- gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
- gdtPtr.Limit = sizeof (GdtTemplate) - 1;
- AsmWriteGdtr (&gdtPtr);
+ LoadGdt(Gdt, GdtSize);
//
// Update selector (segment) registers base on new GDT
@@ -197,4 +214,3 @@
SetCodeSelector ((UINT16)CPU_CODE_SEL);
SetDataSelectors ((UINT16)CPU_DATA_SEL);
}
-
Index: UefiCpuPkg/CpuDxe/CpuDxe.c
===================================================================
--- UefiCpuPkg/CpuDxe/CpuDxe.c (revision 9332)
+++ UefiCpuPkg/CpuDxe/CpuDxe.c (working copy)
@@ -14,11 +14,14 @@
#include "CpuDxe.h"
+EFI_EVENT mEfiVirtualNotifyEvent;
+EFI_PHYSICAL_ADDRESS HandyCpuPage;
+IA32_IDT_GATE_DESCRIPTOR* Idt;
+UINT32 IdtSize;
+
//
// Global Variables
//
-IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };
-
EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];
BOOLEAN InterruptState = FALSE;
EFI_HANDLE mCpuHandle = NULL;
@@ -1004,8 +1007,6 @@
)
{
EFI_STATUS Status;
- VOID *IdtPtrAlignmentBuffer;
- IA32_DESCRIPTOR *IdtPtr;
UINTN Index;
UINTN CurrentHandler;
@@ -1015,27 +1016,33 @@
// Initialize IDT
//
CurrentHandler = (UINTN)AsmIdtVector00;
+
+ //
+ // Allocate Runtime Data for the IDT
+ //
+ IdtSize = INTERRUPT_VECTOR_NUMBER*sizeof(IA32_IDT_GATE_DESCRIPTOR);
+#if 0
+ Idt = AllocateRuntimePool (IdtSize + 16);
+ ASSERT (Idt != NULL);
+ Idt = ALIGN_POINTER (Idt, 16);
+#else
+ Idt = (VOID*)(UINTN)HandyCpuPage + 0x500;
+#endif
+
for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++, CurrentHandler += 0x08) {
- gIdtTable[Index].Bits.OffsetLow = (UINT16)CurrentHandler;
- gIdtTable[Index].Bits.Selector = AsmReadCs();
- gIdtTable[Index].Bits.Reserved_0 = 0;
- gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
- gIdtTable[Index].Bits.OffsetHigh = (UINT16)(CurrentHandler >> 16);
+ Idt[Index].Bits.OffsetLow = (UINT16)CurrentHandler;
+ Idt[Index].Bits.Selector = AsmReadCs();
+ Idt[Index].Bits.Reserved_0 = 0;
+ Idt[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+ Idt[Index].Bits.OffsetHigh = (UINT16)(CurrentHandler >> 16);
#if defined (MDE_CPU_X64)
- gIdtTable[Index].Bits.OffsetUpper = (UINT32)(CurrentHandler >> 32);
- gIdtTable[Index].Bits.Reserved_1 = 0;
+ Idt[Index].Bits.OffsetUpper = (UINT32)(CurrentHandler >> 32);
+ Idt[Index].Bits.Reserved_1 = 0;
#endif
}
- //
- // Load IDT Pointer
- //
- IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
- IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
- IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));
- IdtPtr->Limit = sizeof (gIdtTable) - 1;
- AsmWriteIdtr (IdtPtr);
- FreePool (IdtPtrAlignmentBuffer);
+ // Load IDT
+ LoadIdt(Idt, IdtSize);
//
// Initialize Exception Handlers
@@ -1052,7 +1059,50 @@
}
+VOID EFIAPI
+LoadIdt(VOID* Idt, UINT32 IdtSize)
+{
+ IA32_DESCRIPTOR IdtPtr;
+ IdtPtr.Base = (UINT32)(((UINTN) Idt) & (BASE_4GB-1));
+ IdtPtr.Limit = IdtSize - 1;
+ AsmWriteIdtr (&IdtPtr);
+}
+
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ return Value;
+}
+
+VOID
+EFIAPI
+CpuLibVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_RUNTIME_SERVICES * rs = (EFI_RUNTIME_SERVICES *)Context;
+
+ rs->ConvertPointer (0, (VOID **) &Gdt);
+ rs->ConvertPointer (0, (VOID **) &Idt);
+
+ DisableInterrupts();
+
+ LoadIdt(Idt, IdtSize);
+ LoadGdt(Gdt, GdtSize);
+
+ //IoWrite32(0xef11, 1);
+}
+
+extern EFI_GUID gEfiEventVirtualAddressChangeGuid;
+
+
/**
Initialize the state information for the CPU Architectural Protocol.
@@ -1073,6 +1123,17 @@
{
EFI_STATUS Status;
+
+ // Allocate handy page
+ HandyCpuPage = 0xffffffff;
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiReservedMemoryType,
+ 1,
+ &HandyCpuPage );
+ ASSERT_EFI_ERROR (Status);
+ ASSERT (HandyCpuPage != 0xffffffff);
+
//
// Make sure interrupts are disabled
//
@@ -1103,6 +1164,18 @@
//
RefreshGcdMemoryAttributes ();
+
+ // Register virtual address change notifier
+#if 0
+ gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ CpuLibVirtualNotifyEvent,
+ SystemTable->RuntimeServices,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mEfiVirtualNotifyEvent
+ );
+#endif
+
return Status;
}
-
Index: UefiCpuPkg/CpuDxe/CpuDxe.h
===================================================================
--- UefiCpuPkg/CpuDxe/CpuDxe.h (revision 9332)
+++ UefiCpuPkg/CpuDxe/CpuDxe.h (working copy)
@@ -136,5 +136,17 @@
);
+VOID EFIAPI
+LoadGdt(VOID* Gdt, UINT32 GdtSize);
+
+VOID EFIAPI
+LoadIdt(VOID* Idt, UINT32 IdtSize);
+
+extern EFI_PHYSICAL_ADDRESS HandyCpuPage;
+extern VOID* Gdt;
+extern UINT32 GdtSize;
+extern IA32_IDT_GATE_DESCRIPTOR* Idt;
+extern UINT32 IdtSize;
+
#endif

4
CloverPkg.dec
View File

@ -133,7 +133,11 @@
## Include/Microsoft/Guid/MicrosoftVariable.h
gMicrosoftVariableGuid = {0x77FA9ABD, 0x0359, 0x4D32, {0xBD, 0x60, 0x28, 0xF4, 0xE7, 0x8F, 0x78, 0x4B}}
##OsxAptioFixDrv
gEfiMiscSubClassGuid = {0x772484B2, 0x7482, 0x4b91, {0x9F, 0x9A, 0xAD, 0x43, 0xF8, 0x1C, 0x58, 0x81}}
##Oc
gEfiMemorySubClassGuid = { 0x4E8F4EBB, 0x64B9, 0x4e05, { 0x9b, 0x18, 0x4c, 0xfe, 0x49, 0x23, 0x50, 0x97 }}
[Protocols]

4
Drivers/UsbKbDxe/KeyBoard.c
View File

@ -984,7 +984,7 @@ KeyboardHandler (
UINT32 UsbStatus;
EFI_KEY_DESCRIPTOR *KeyDescriptor;
UINTN NumberOfKeys;
APPLE_KEY Keys[8];
APPLE_KEY_CODE Keys[8];
ASSERT (Context != NULL);
@ -1104,7 +1104,7 @@ KeyboardHandler (
UsbKeyboardDevice->KeyMapDbIndex,
(APPLE_MODIFIER_MAP)CurModifierMap,
NumberOfKeys,
&Keys[0] //APPLE_KEY
&Keys[0] //APPLE_KEY_CODE
);
}

2
FileSystems/GrubFS/grub/grub-core/fs/reiserfs.c
View File

@ -65,7 +65,7 @@ GRUB_MOD_LICENSE ("GPLv3+");
static grub_dl_t my_mod;
#define assert(boolean) real_assert (boolean, GRUB_FILE, __LINE__)
#define assert(boolean) real_assert (boolean, GRUB_STRINGIFY(GRUB_FILE), __LINE__)
static inline void
real_assert (int boolean, const char *file, const int line)
{

2
FileSystems/GrubFS/grub/grub-core/kern/mm.c
View File

@ -412,7 +412,7 @@ grub_free (void *ptr)
do
{
grub_printf ("%s:%d: q=%p, q->size=0x%x, q->magic=0x%x\n",
GRUB_FILE, __LINE__, q, q->size, q->magic);
GRUB_STRINGIFY(GRUB_FILE), __LINE__, q, q->size, q->magic);
q = q->next;
}
while (q != r->first);

3
FileSystems/GrubFS/grub/include/grub/list.h
View File

@ -23,6 +23,7 @@
#include <grub/symbol.h>
#include <grub/err.h>
#include <grub/compiler.h>
#include <grub/misc.h>
struct grub_list
{
@ -48,7 +49,7 @@ grub_bad_type_cast_real (int line, const char *file)
file, line);
}
#define grub_bad_type_cast() grub_bad_type_cast_real(__LINE__, GRUB_FILE)
#define grub_bad_type_cast() grub_bad_type_cast_real(__LINE__, GRUB_STRINGIFY(GRUB_FILE))
#define GRUB_FIELD_MATCH(ptr, type, field) \
((char *) &(ptr)->field == (char *) &((type) (ptr))->field)

6
FileSystems/GrubFS/grub/include/grub/misc.h
View File

@ -62,7 +62,9 @@
//#define ARRAY_SIZE(array) (sizeof (array) / sizeof (array[0])) //defined in edk2
#define COMPILE_TIME_ASSERT(cond) switch (0) { case 1: case !(cond): ; }
#define grub_dprintf(condition, ...) grub_real_dprintf(GRUB_FILE, __LINE__, condition, __VA_ARGS__)
#define _GRUB_STRINGIFY(x) #x
#define GRUB_STRINGIFY(x) _GRUB_STRINGIFY(x)
#define grub_dprintf(condition, ...) grub_real_dprintf(GRUB_STRINGIFY(GRUB_FILE), __LINE__, condition, __VA_ARGS__)
#undef grub_memmove
#define grub_memmove memmove
@ -550,7 +552,7 @@ extern struct grub_boot_time *EXPORT_VAR(grub_boot_time_head);
void EXPORT_FUNC(grub_real_boot_time) (const char *file,
const int line,
const char *fmt, ...) __attribute__ ((format (GNU_PRINTF, 3, 4)));
#define grub_boot_time(...) grub_real_boot_time(GRUB_FILE, __LINE__, __VA_ARGS__)
#define grub_boot_time(...) grub_real_boot_time(GRUB_STRINGIFY(GRUB_FILE), __LINE__, __VA_ARGS__)
#else
#define grub_boot_time(...)
#endif

12
FileSystems/GrubFS/grub/include/grub/mm.h
View File

@ -38,7 +38,7 @@ void *EXPORT_FUNC(grub_memalign) (grub_size_t align, grub_size_t size);
#endif
void grub_mm_check_real (const char *file, int line);
#define grub_mm_check() grub_mm_check_real (GRUB_FILE, __LINE__);
#define grub_mm_check() grub_mm_check_real (GRUB_STRINGIFY(GRUB_FILE), __LINE__);
/* For debugging. */
#if defined(MM_DEBUG) && !defined(GRUB_UTIL) && !defined (GRUB_MACHINE_EMU)
@ -49,19 +49,19 @@ void grub_mm_dump_free (void);
void grub_mm_dump (unsigned lineno);
#define grub_malloc(size) \
grub_debug_malloc (GRUB_FILE, __LINE__, size)
grub_debug_malloc (GRUB_STRINGIFY(GRUB_FILE), __LINE__, size)
#define grub_zalloc(size) \
grub_debug_zalloc (GRUB_FILE, __LINE__, size)
grub_debug_zalloc (GRUB_STRINGIFY(GRUB_FILE), __LINE__, size)
#define grub_realloc(ptr,size) \
grub_debug_realloc (GRUB_FILE, __LINE__, ptr, size)
grub_debug_realloc (GRUB_STRINGIFY(GRUB_FILE), __LINE__, ptr, size)
#define grub_memalign(align,size) \
grub_debug_memalign (GRUB_FILE, __LINE__, align, size)
grub_debug_memalign (GRUB_STRINGIFY(GRUB_FILE), __LINE__, align, size)
#define grub_free(ptr) \
grub_debug_free (GRUB_FILE, __LINE__, ptr)
grub_debug_free (GRUB_STRINGIFY(GRUB_FILE), __LINE__, ptr)
void *EXPORT_FUNC(grub_debug_malloc) (const char *file, int line,
grub_size_t size);

2
FileSystems/GrubFS/grub/include/grub/test.h
View File

@ -67,7 +67,7 @@ void grub_test_assert_helper (int cond, const char *file,
__attribute__ ((format (GNU_PRINTF, 6, 7)));
#define grub_test_assert(cond, ...) \
grub_test_assert_helper(cond, GRUB_FILE, __FUNCTION__, __LINE__, \
grub_test_assert_helper(cond, GRUB_STRINGIFY(GRUB_FILE), __FUNCTION__, __LINE__, \
#cond, ## __VA_ARGS__);
void grub_unit_test_init (void);

8
FileSystems/GrubFS/src/AFFS.inf
View File

@ -71,8 +71,8 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFFS.efi\" -DDRIVERNAME=affs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFFS.efi\" -DDRIVERNAME=affs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFFS.efi\" -DDRIVERNAME=affs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFFS.efi\" -DDRIVERNAME=affs -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFFS.efi -DDRIVERNAME=affs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFFS.efi -DDRIVERNAME=affs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFFS.efi -DDRIVERNAME=affs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFFS.efi -DDRIVERNAME=affs -Os

8
FileSystems/GrubFS/src/AFS.inf
View File

@ -71,7 +71,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFS.efi\" -DDRIVERNAME=afs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFS.efi\" -DDRIVERNAME=afs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFS.efi\" -DDRIVERNAME=afs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"AFS.efi\" -DDRIVERNAME=afs -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFS.efi -DDRIVERNAME=afs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFS.efi -DDRIVERNAME=afs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFS.efi -DDRIVERNAME=afs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=AFS.efi -DDRIVERNAME=afs -Os

8
FileSystems/GrubFS/src/BFS.inf
View File

@ -71,7 +71,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BFS.efi\" -DDRIVERNAME=bfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BFS.efi\" -DDRIVERNAME=bfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BFS.efi\" -DDRIVERNAME=bfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BFS.efi\" -DDRIVERNAME=bfs -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BFS.efi -DDRIVERNAME=bfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BFS.efi -DDRIVERNAME=bfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BFS.efi -DDRIVERNAME=bfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BFS.efi -DDRIVERNAME=bfs -Os

8
FileSystems/GrubFS/src/BTRFS.inf
View File

@ -75,7 +75,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BTRFS.efi\" -DDRIVERNAME=btrfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BTRFS.efi\" -DDRIVERNAME=btrfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BTRFS.efi\" -DDRIVERNAME=btrfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"BTRFS.efi\" -DDRIVERNAME=btrfs -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BTRFS.efi -DDRIVERNAME=btrfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BTRFS.efi -DDRIVERNAME=btrfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BTRFS.efi -DDRIVERNAME=btrfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=BTRFS.efi -DDRIVERNAME=btrfs -Os

8
FileSystems/GrubFS/src/CBFS.inf
View File

@ -74,7 +74,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CBFS.efi\" -DDRIVERNAME=cbfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CBFS.efi\" -DDRIVERNAME=cbfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CBFS.efi\" -DDRIVERNAME=cbfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CBFS.efi\" -DDRIVERNAME=cbfs -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CBFS.efi -DDRIVERNAME=cbfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CBFS.efi -DDRIVERNAME=cbfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CBFS.efi -DDRIVERNAME=cbfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CBFS.efi -DDRIVERNAME=cbfs -Os

8
FileSystems/GrubFS/src/CPIO.inf
View File

@ -72,7 +72,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO.efi\" -DDRIVERNAME=cpio -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO.efi\" -DDRIVERNAME=cpio -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO.efi\" -DDRIVERNAME=cpio -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO.efi\" -DDRIVERNAME=cpio -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO.efi -DDRIVERNAME=cpio -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO.efi -DDRIVERNAME=cpio -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO.efi -DDRIVERNAME=cpio -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO.efi -DDRIVERNAME=cpio -Os

8
FileSystems/GrubFS/src/CPIO_BE.inf
View File

@ -72,7 +72,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO_BE.efi\" -DDRIVERNAME=cpio_be -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO_BE.efi\" -DDRIVERNAME=cpio_be -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO_BE.efi\" -DDRIVERNAME=cpio_be -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"CPIO_BE.efi\" -DDRIVERNAME=cpio_be -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO_BE.efi -DDRIVERNAME=cpio_be -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO_BE.efi -DDRIVERNAME=cpio_be -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO_BE.efi -DDRIVERNAME=cpio_be -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=CPIO_BE.efi -DDRIVERNAME=cpio_be -Os

8
FileSystems/GrubFS/src/EXFAT.inf
View File

@ -72,9 +72,9 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32 -DMODE_EXFAT
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64 -DMODE_EXFAT
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXFAT.efi\" -DDRIVERNAME=exfat -O0
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXFAT.efi\" -DDRIVERNAME=exfat -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXFAT.efi\" -DDRIVERNAME=exfat -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXFAT.efi\" -DDRIVERNAME=exfat -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXFAT.efi -DDRIVERNAME=exfat -O0
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXFAT.efi -DDRIVERNAME=exfat -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXFAT.efi -DDRIVERNAME=exfat -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXFAT.efi -DDRIVERNAME=exfat -Os

8
FileSystems/GrubFS/src/EXT2.inf
View File

@ -71,7 +71,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXT2.efi\" -DDRIVERNAME=ext2 -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXT2.efi\" -DDRIVERNAME=ext2 -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXT2.efi\" -DDRIVERNAME=ext2 -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"EXT2.efi\" -DDRIVERNAME=ext2 -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXT2.efi -DDRIVERNAME=ext2 -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXT2.efi -DDRIVERNAME=ext2 -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXT2.efi -DDRIVERNAME=ext2 -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=EXT2.efi -DDRIVERNAME=ext2 -Os

8
FileSystems/GrubFS/src/FAT.inf
View File

@ -71,7 +71,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"FAT.efi\" -DDRIVERNAME=fat -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"FAT.efi\" -DDRIVERNAME=fat -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"FAT.efi\" -DDRIVERNAME=fat -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"FAT.efi\" -DDRIVERNAME=fat -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=FAT.efi -DDRIVERNAME=fat -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=FAT.efi -DDRIVERNAME=fat -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=FAT.efi -DDRIVERNAME=fat -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=FAT.efi -DDRIVERNAME=fat -Os

8
FileSystems/GrubFS/src/HFS.inf
View File

@ -71,7 +71,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFS.efi\" -DDRIVERNAME=hfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFS.efi\" -DDRIVERNAME=hfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFS.efi\" -DDRIVERNAME=hfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFS.efi\" -DDRIVERNAME=hfs -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFS.efi -DDRIVERNAME=hfs -Os
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFS.efi -DDRIVERNAME=hfs -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFS.efi -DDRIVERNAME=hfs -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFS.efi -DDRIVERNAME=hfs -Os

8
FileSystems/GrubFS/src/HFSPLUS.inf
View File

@ -74,8 +74,8 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFSPLUS.efi\" -DDRIVERNAME=hfsplus -O0
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFSPLUS.efi\" -DDRIVERNAME=hfsplus -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFSPLUS.efi\" -DDRIVERNAME=hfsplus -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"HFSPLUS.efi\" -DDRIVERNAME=hfsplus -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFSPLUS.efi -DDRIVERNAME=hfsplus -O0
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFSPLUS.efi -DDRIVERNAME=hfsplus -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFSPLUS.efi -DDRIVERNAME=hfsplus -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=HFSPLUS.efi -DDRIVERNAME=hfsplus -Os

8
FileSystems/GrubFS/src/ISO9660.inf
View File

@ -72,7 +72,7 @@
[BuildOptions.common]
*_*_IA32_CC_FLAGS = -DFORMAT=efi-app-ia32
*_*_X64_CC_FLAGS = -DFORMAT=efi-app-x64
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"ISO9660.efi\" -DDRIVERNAME=iso9660 -O0
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"ISO9660.efi\" -DDRIVERNAME=iso9660 -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"ISO9660.efi\" -DDRIVERNAME=iso9660 -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=\"ISO9660.efi\" -DDRIVERNAME=iso9660 -Os
GCC:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=ISO9660.efi -DDRIVERNAME=iso9660 -O0
XCODE:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=ISO9660.efi -DDRIVERNAME=iso9660 -Os
IBTEL:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=ISO9660.efi -DDRIVERNAME=iso9660 -Os
MSFT:*_*_*_CC_FLAGS = -DCPU_$(ARCH) -DMDEPKG_NDEBUG -DGRUB_MACHINE_EFI -DGRUB_KERNEL -DGRUB_UTIL -DGRUB_FILE=ISO9660.efi -DDRIVERNAME=iso9660 -Os

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