mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-29 12:35:53 +01:00
177 lines
4.9 KiB
NASM
177 lines
4.9 KiB
NASM
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SmiException.nasm
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;
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; Abstract:
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;
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; Exception handlers used in SM mode
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;
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;-------------------------------------------------------------------------------
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%include "StuffRsbNasm.inc"
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global ASM_PFX(gcStmPsd)
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extern ASM_PFX(SmmStmExceptionHandler)
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extern ASM_PFX(SmmStmSetup)
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extern ASM_PFX(SmmStmTeardown)
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extern ASM_PFX(gStmXdSupported)
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extern ASM_PFX(gStmSmiHandlerIdtr)
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%define MSR_IA32_MISC_ENABLE 0x1A0
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%define MSR_EFER 0xc0000080
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%define MSR_EFER_XD 0x800
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CODE_SEL equ 0x38
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DATA_SEL equ 0x20
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TR_SEL equ 0x40
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SECTION .data
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;
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; This structure serves as a template for all processors.
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;
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ASM_PFX(gcStmPsd):
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DB 'TXTPSSIG'
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DW PSD_SIZE
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DW 1 ; Version
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DD 0 ; LocalApicId
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DB 0x0F ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
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DB 0 ; BIOS to STM
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DB 0 ; STM to BIOS
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DB 0
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DW CODE_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW TR_SEL
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DW 0
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DQ 0 ; SmmCr3
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DQ ASM_PFX(OnStmSetup)
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DQ ASM_PFX(OnStmTeardown)
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DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
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DQ 0 ; SmmSmiHandlerRsp
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DQ 0
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DD 0
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DD 0x80010100 ; RequiredStmSmmRevId
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DQ ASM_PFX(OnException)
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DQ 0 ; ExceptionStack
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DW DATA_SEL
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DW 0x01F ; ExceptionFilter
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DD 0
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DQ 0
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DQ 0 ; BiosHwResourceRequirementsPtr
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DQ 0 ; AcpiRsdp
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DB 0 ; PhysicalAddressBits
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PSD_SIZE equ $ - ASM_PFX(gcStmPsd)
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; SMM Exception handlers
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;------------------------------------------------------------------------------
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global ASM_PFX(OnException)
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ASM_PFX(OnException):
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mov rcx, rsp
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add rsp, -0x28
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call ASM_PFX(SmmStmExceptionHandler)
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add rsp, 0x28
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mov ebx, eax
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mov eax, 4
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vmcall
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jmp $
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global ASM_PFX(OnStmSetup)
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ASM_PFX(OnStmSetup):
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;
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; Check XD disable bit
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;
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xor r8, r8
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lea rax, [ASM_PFX(gStmXdSupported)]
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mov al, [rax]
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cmp al, 0
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jz @StmXdDone1
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .01
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.01:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone1:
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push r8
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add rsp, -0x20
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call ASM_PFX(SmmStmSetup)
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add rsp, 0x20
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lea rax, [ASM_PFX(gStmXdSupported)]
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mov al, [rax]
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cmp al, 0
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jz .11
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pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz .11
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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.11:
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StuffRsb64
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rsm
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global ASM_PFX(OnStmTeardown)
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ASM_PFX(OnStmTeardown):
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;
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; Check XD disable bit
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;
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xor r8, r8
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lea rax, [ASM_PFX(gStmXdSupported)]
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mov al, [rax]
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cmp al, 0
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jz @StmXdDone2
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .02
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.02:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone2:
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push r8
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add rsp, -0x20
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call ASM_PFX(SmmStmTeardown)
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add rsp, 0x20
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lea rax, [ASM_PFX(gStmXdSupported)]
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mov al, [rax]
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cmp al, 0
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jz .12
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pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz .12
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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.12:
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StuffRsb64
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rsm
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