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update xhci from edk2

Browse Source 
Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
SergeySlice 2022-07-01 20:05:01 +03:00
parent cb4f2d0544
commit 02999f3763
10 changed files with 2782 additions and 2362 deletions
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23
MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c
View File

@ -21,15 +21,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName =
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) XhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) XhciComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)XhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)XhciComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
{ "eng;en", L"Usb Xhci Driver" },
{ NULL , NULL }
{ NULL, NULL }
};
/**
@ -166,9 +166,9 @@ XhciComponentNameGetControllerName (
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
USB_XHCI_INSTANCE *XhciDev;
EFI_STATUS Status;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
USB_XHCI_INSTANCE *XhciDev;
//
// This is a device driver, so ChildHandle must be NULL.
@ -185,7 +185,7 @@ XhciComponentNameGetControllerName (
gXhciDriverBinding.DriverBindingHandle,
&gEfiPciIoProtocolGuid
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@ -195,12 +195,12 @@ XhciComponentNameGetControllerName (
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
(VOID **) &Usb2Hc,
(VOID **)&Usb2Hc,
gXhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@ -213,5 +213,4 @@ XhciComponentNameGetControllerName (
ControllerName,
(BOOLEAN)(This == &gXhciComponentName)
);
}

2
MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h
View File

@ -57,7 +57,6 @@ XhciComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@ -137,4 +136,3 @@ XhciComponentNameGetControllerName (
);
#endif

281
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
View File

@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Xhci.h"
/**
Allocate a block of memory to be used by the buffer pool.
@ -22,21 +20,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
PciIo = Pool->PciIo;
Block = AllocateZeroPool(sizeof (USBHC_MEM_BLOCK));
Block = AllocateZeroPool (sizeof (USBHC_MEM_BLOCK));
if (Block == NULL) {
return NULL;
}
@ -47,12 +45,12 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool(Block->BitsLen);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool(Block);
gBS->FreePool (Block);
return NULL;
}
@ -69,11 +67,11 @@ UsbHcAllocMemBlock (
0
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto FREE_BITARRAY;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@ -83,13 +81,13 @@ UsbHcAllocMemBlock (
&Mapping
);
if (EFI_ERROR(Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
goto FREE_BUFFER;
}
Block->BufHost = BufHost;
Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
Block->Mapping = Mapping;
Block->BufHost = BufHost;
Block->Buf = (UINT8 *)((UINTN)MappedAddr);
Block->Mapping = Mapping;
return Block;
@ -97,12 +95,11 @@ FREE_BUFFER:
PciIo->FreeBuffer (PciIo, Pages, BufHost);
FREE_BITARRAY:
gBS->FreePool(Block->Bits);
gBS->FreePool(Block);
gBS->FreePool (Block->Bits);
gBS->FreePool (Block);
return NULL;
}
/**
Free the memory block from the memory pool.
@ -112,11 +109,11 @@ FREE_BITARRAY:
**/
VOID
UsbHcFreeMemBlock (
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@ -128,11 +125,10 @@ UsbHcFreeMemBlock (
PciIo->Unmap (PciIo, Block->Mapping);
PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (Block->BufLen), Block->BufHost);
gBS->FreePool(Block->Bits);
gBS->FreePool(Block);
gBS->FreePool (Block->Bits);
gBS->FreePool (Block);
}
/**
Alloc some memory from the block.
@ -145,22 +141,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@ -176,13 +172,12 @@ UsbHcAllocMemFromBlock (
}
NEXT_BIT (Byte, Bit);
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
@ -193,13 +188,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@ -218,16 +213,16 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@ -241,7 +236,7 @@ UsbHcGetPciAddrForHostAddr (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@ -250,8 +245,8 @@ UsbHcGetPciAddrForHostAddr (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@ -267,16 +262,16 @@ UsbHcGetPciAddrForHostAddr (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS HostAddr;
UINTN Offset;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS HostAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@ -290,7 +285,7 @@ UsbHcGetHostAddrForPciAddr (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
if ((Block->Buf <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
@ -299,8 +294,8 @@ UsbHcGetHostAddrForPciAddr (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->Buf;
HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->BufHost + Offset);
Offset = (UINT8 *)Mem - Block->Buf;
HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->BufHost + Offset);
return HostAddr;
}
@ -313,8 +308,8 @@ UsbHcGetHostAddrForPciAddr (
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@ -322,7 +317,6 @@ UsbHcInsertMemBlockToPool (
Head->Next = Block;
}
/**
Is the memory block empty?
@ -334,10 +328,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@ -348,7 +342,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
/**
Unlink the memory block from the pool's list.
@ -358,11 +351,11 @@ UsbHcIsMemBlockEmpty (
**/
VOID
UsbHcUnlinkMemBlock (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@ -375,7 +368,6 @@ UsbHcUnlinkMemBlock (
}
}
/**
Initialize the memory management pool for the host controller.
@ -390,7 +382,7 @@ UsbHcInitMemPool (
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
USBHC_MEM_POOL *Pool;
USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@ -398,18 +390,17 @@ UsbHcInitMemPool (
return Pool;
}
Pool->PciIo = PciIo;
Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
Pool->PciIo = PciIo;
Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
gBS->FreePool(Pool);
gBS->FreePool (Pool);
Pool = NULL;
}
return Pool;
}
/**
Release the memory management pool.
@ -421,10 +412,10 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@ -439,11 +430,10 @@ UsbHcFreeMemPool (
}
UsbHcFreeMemBlock (Pool, Pool->Head);
gBS->FreePool(Pool);
gBS->FreePool (Pool);
return EFI_SUCCESS;
}
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@ -456,16 +446,16 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@ -503,7 +493,7 @@ UsbHcAllocateMem (
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
DEBUG ((DEBUG_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}
@ -520,7 +510,6 @@ UsbHcAllocateMem (
return Mem;
}
/**
Free the allocated memory back to the memory pool.
@ -531,22 +520,22 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@ -557,8 +546,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@ -566,7 +555,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@ -589,7 +578,7 @@ UsbHcFreeMem (
UsbHcFreeMemBlock (Pool, Block);
}
return ;
return;
}
/**
@ -621,13 +610,13 @@ UsbHcAllocateAlignedPages (
OUT VOID **Mapping
)
{
EFI_STATUS Status;
VOID *Memory;
UINTN AlignedMemory;
UINTN AlignmentMask;
UINTN UnalignedPages;
UINTN RealPages;
UINTN Bytes;
EFI_STATUS Status;
VOID *Memory;
UINTN AlignedMemory;
UINTN AlignmentMask;
UINTN UnalignedPages;
UINTN RealPages;
UINTN Bytes;
//
// Alignment must be a power of two or zero.
@ -641,12 +630,13 @@ UsbHcAllocateAlignedPages (
if (Pages == 0) {
return EFI_INVALID_PARAMETER;
}
if (Alignment > EFI_PAGE_SIZE) {
//
// Calculate the total number of pages since alignment is larger than page size.
//
AlignmentMask = Alignment - 1;
RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
AlignmentMask = Alignment - 1;
RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
//
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
@ -656,22 +646,24 @@ UsbHcAllocateAlignedPages (
PciIo,
AllocateAnyPages,
EfiBootServicesData,
Pages,
RealPages,
&Memory,
0
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
//
Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
ASSERT_EFI_ERROR(Status);
ASSERT_EFI_ERROR (Status);
}
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@ -679,7 +671,7 @@ UsbHcAllocateAlignedPages (
// Free last unaligned page(s).
//
Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
ASSERT_EFI_ERROR(Status);
ASSERT_EFI_ERROR (Status);
}
} else {
//
@ -693,28 +685,29 @@ UsbHcAllocateAlignedPages (
&Memory,
0
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
AlignedMemory = (UINTN) Memory;
AlignedMemory = (UINTN)Memory;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
(VOID *) AlignedMemory,
(VOID *)AlignedMemory,
&Bytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR(Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *) AlignedMemory);
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *)AlignedMemory);
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *) AlignedMemory;
*HostAddress = (VOID *)AlignedMemory;
return EFI_SUCCESS;
}
@ -730,23 +723,23 @@ UsbHcAllocateAlignedPages (
**/
VOID
UsbHcFreeAlignedPages (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *HostAddress,
IN UINTN Pages,
VOID *Mapping
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *HostAddress,
IN UINTN Pages,
VOID *Mapping
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Pages != 0);
Status = PciIo->Unmap (PciIo, Mapping);
ASSERT_EFI_ERROR(Status);
ASSERT_EFI_ERROR (Status);
Status = PciIo->FreeBuffer (
PciIo,
Pages,
HostAddress
);
ASSERT_EFI_ERROR(Status);
ASSERT_EFI_ERROR (Status);
}

63
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
View File

@ -10,20 +10,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_XHCI_MEM_H_
#define _EFI_XHCI_MEM_H_
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
@ -32,16 +32,16 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@ -60,8 +60,6 @@ typedef struct _USBHC_MEM_POOL {
} \
} while (0)
/**
Initialize the memory management pool for the host controller.
@ -76,7 +74,6 @@ UsbHcInitMemPool (
IN EFI_PCI_IO_PROTOCOL *PciIo
);
/**
Release the memory management pool.
@ -88,10 +85,9 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
);
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@ -104,11 +100,10 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
);
/**
Free the allocated memory back to the memory pool.
@ -119,9 +114,9 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@ -136,9 +131,9 @@ UsbHcFreeMem (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@ -153,9 +148,9 @@ UsbHcGetPciAddrForHostAddr (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@ -198,10 +193,10 @@ UsbHcAllocateAlignedPages (
**/
VOID
UsbHcFreeAlignedPages (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *HostAddress,
IN UINTN Pages,
VOID *Mapping
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *HostAddress,
IN UINTN Pages,
VOID *Mapping
);
#endif

994
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

File diff suppressed because it is too large Load Diff

202
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
View File

@ -3,6 +3,7 @@
Provides some data structure definitions used by the XHCI host controller driver.
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -28,8 +29,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/Pci.h>
typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "XhciReg.h"
#include "XhciSched.h"
@ -39,70 +40,62 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
// The unit is microsecond, setting it as 1us.
//
#define XHC_1_MICROSECOND (1)
#define XHC_1_MICROSECOND (1)
//
// The unit is microsecond, setting it as 1ms.
//
#define XHC_1_MILLISECOND (1000)
#define XHC_1_MILLISECOND (1000)
//
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
#define XHC_GENERIC_TIMEOUT (10 * 1000)
#define XHC_GENERIC_TIMEOUT (10 * 1000)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
#define XHC_RESET_TIMEOUT (1000)
#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// XHC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//
#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// XHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
#define XHC_TPL TPL_NOTIFY
#define XHC_TPL TPL_NOTIFY
#define CMD_RING_TRB_NUMBER 0x100
#define TR_RING_TRB_NUMBER 0x100
#define ERST_NUMBER 0x01
#define EVENT_RING_TRB_NUMBER 0x200
#define CMD_RING_TRB_NUMBER 0x100
#define TR_RING_TRB_NUMBER 0x100
#define ERST_NUMBER 0x01
#define EVENT_RING_TRB_NUMBER 0x200
#define CMD_INTER 0
#define CTRL_INTER 1
#define BULK_INTER 2
#define INT_INTER 3
#define INT_INTER_ASYNC 4
#define CMD_INTER 0
#define CTRL_INTER 1
#define BULK_INTER 2
#define INT_INTER 3
#define INT_INTER_ASYNC 4
//
// Iterate through the double linked list. This is delete-safe.
// Don't touch NextEntry
//
#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \
for (Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(Xhc, Offset, Bit) \
(XHC_BIT_IS_SET(XhcReadOpReg ((Xhc), (Offset)), (Bit)))
#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
#define USB_DESC_TYPE_HUB 0x29
#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a
@ -120,19 +113,19 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
#pragma pack(1)
typedef struct {
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
UINT8 Length;
UINT8 DescType;
UINT8 NumPorts;
UINT16 HubCharacter;
UINT8 PwrOn2PwrGood;
UINT8 HubContrCurrent;
UINT8 Filler[16];
UINT8 Length;
UINT8 DescType;
UINT8 NumPorts;
UINT16 HubCharacter;
UINT8 PwrOn2PwrGood;
UINT8 HubContrCurrent;
UINT8 Filler[16];
} EFI_USB_HUB_DESCRIPTOR;
#pragma pack()
@ -140,23 +133,23 @@ struct _USB_DEV_CONTEXT {
//
// Whether this entry in UsbDevContext array is used or not.
//
BOOLEAN Enabled;
BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
UINT8 SlotId;
UINT8 SlotId;
//
// The route string presented an attached usb device.
//
USB_DEV_ROUTE RouteString;
USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
USB_DEV_ROUTE ParentRouteString;
USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
UINT8 XhciDevAddr;
UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@ -165,23 +158,23 @@ struct _USB_DEV_CONTEXT {
// through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
UINT8 BusDevAddr;
UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
VOID *InputContext;
VOID *InputContext;
//
// The pointer to the output device context.
//
VOID *OutputContext;
VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
VOID *EndpointTransferRing[31];
VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
EFI_USB_DEVICE_DESCRIPTOR DevDesc;
EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@ -189,81 +182,82 @@ struct _USB_DEV_CONTEXT {
// such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
//
// A device has an active Configuration.
//
UINT8 ActiveConfiguration;
UINT8 ActiveConfiguration;
//
// Every interface has an active AlternateSetting.
//
UINT8 *ActiveAlternateSetting;
UINT8 *ActiveAlternateSetting;
};
struct _USB_XHCI_INSTANCE {
UINT32 Signature;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
UINT32 Signature;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
//
// ExitBootServicesEvent is used to set OS semaphore and
// stop the XHC DMA operation after exit boot service.
//
EFI_EVENT ExitBootServiceEvent;
EFI_EVENT PollTimer;
LIST_ENTRY AsyncIntTransfers;
EFI_EVENT ExitBootServiceEvent;
EFI_EVENT PollTimer;
LIST_ENTRY AsyncIntTransfers;
UINT8 CapLength; ///< Capability Register Length
XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
XHC_HCCPARAMS HcCParams; ///< Capability Parameters
UINT32 DBOff; ///< Doorbell Offset
UINT32 RTSOff; ///< Runtime Register Space Offset
UINT16 MaxInterrupt;
UINT32 PageSize;
UINT64 *ScratchBuf;
VOID *ScratchMap;
UINT32 MaxScratchpadBufs;
UINT64 *ScratchEntry;
UINTN *ScratchEntryMap;
UINT32 ExtCapRegBase;
UINT32 UsbLegSupOffset;
UINT32 DebugCapSupOffset;
UINT64 *DCBAA;
VOID *DCBAAMap;
UINT32 MaxSlotsEn;
URB *PendingUrb;
UINT8 CapLength; ///< Capability Register Length
XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
XHC_HCCPARAMS HcCParams; ///< Capability Parameters
UINT32 DBOff; ///< Doorbell Offset
UINT32 RTSOff; ///< Runtime Register Space Offset
UINT16 MaxInterrupt;
UINT32 PageSize;
UINT64 *ScratchBuf;
VOID *ScratchMap;
UINT32 MaxScratchpadBufs;
UINT64 *ScratchEntry;
UINTN *ScratchEntryMap;
UINT32 ExtCapRegBase;
UINT32 UsbLegSupOffset;
UINT32 DebugCapSupOffset;
UINT32 Usb2SupOffset;
UINT32 Usb3SupOffset;
UINT64 *DCBAA;
VOID *DCBAAMap;
UINT32 MaxSlotsEn;
URB *PendingUrb;
//
// Cmd Transfer Ring
//
TRANSFER_RING CmdRing;
TRANSFER_RING CmdRing;
//
// EventRing
//
EVENT_RING EventRing;
EVENT_RING EventRing;
//
// Misc
//
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// Store device contexts managed by XHCI instance
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
USB_DEV_CONTEXT UsbDevContext[256];
USB_DEV_CONTEXT UsbDevContext[256];
BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@ -281,9 +275,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@ -302,9 +296,9 @@ XhcDriverBindingSupported (
EFI_STATUS
EFIAPI
XhcDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@ -323,10 +317,10 @@ XhcDriverBindingStart (
EFI_STATUS
EFIAPI
XhcDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
/**

467
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
View File

@ -21,24 +21,24 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UINT8
XhcReadCapReg8 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
)
{
UINT8 Data;
EFI_STATUS Status;
UINT8 Data;
EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint8,
XHC_BAR_INDEX,
(UINT64) Offset,
(UINT64)Offset,
1,
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFF;
}
@ -57,24 +57,24 @@ XhcReadCapReg8 (
**/
UINT32
XhcReadCapReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
(UINT64) Offset,
(UINT64)Offset,
1,
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@ -93,12 +93,12 @@ XhcReadCapReg (
**/
UINT32
XhcReadOpReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@ -111,8 +111,8 @@ XhcReadOpReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@ -129,12 +129,12 @@ XhcReadOpReg (
**/
VOID
XhcWriteOpReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@ -147,15 +147,11 @@ XhcWriteOpReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
/**
Write the data to the XHCI door bell register.
@ -166,12 +162,12 @@ XhcWriteOpReg (
**/
VOID
XhcWriteDoorBellReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Xhc->DBOff != 0);
@ -184,8 +180,8 @@ XhcWriteDoorBellReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@ -200,12 +196,12 @@ XhcWriteDoorBellReg (
**/
UINT32
XhcReadRuntimeReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@ -218,8 +214,8 @@ XhcReadRuntimeReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@ -236,12 +232,12 @@ XhcReadRuntimeReg (
**/
VOID
XhcWriteRuntimeReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@ -254,8 +250,8 @@ XhcWriteRuntimeReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@ -270,12 +266,12 @@ XhcWriteRuntimeReg (
**/
UINT32
XhcReadExtCapReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@ -288,8 +284,8 @@ XhcReadExtCapReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@ -306,12 +302,12 @@ XhcReadExtCapReg (
**/
VOID
XhcWriteExtCapReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@ -324,12 +320,11 @@ XhcWriteExtCapReg (
&Data
);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
/**
Set one bit of the runtime register while keeping other bits.
@ -340,12 +335,12 @@ XhcWriteExtCapReg (
**/
VOID
XhcSetRuntimeRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data |= Bit;
@ -362,12 +357,12 @@ XhcSetRuntimeRegBit (
**/
VOID
XhcClearRuntimeRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data &= ~Bit;
@ -384,19 +379,18 @@ XhcClearRuntimeRegBit (
**/
VOID
XhcSetOpRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data |= Bit;
XhcWriteOpReg (Xhc, Offset, Data);
}
/**
Clear one bit of the operational register while keeping other bits.
@ -407,12 +401,12 @@ XhcSetOpRegBit (
**/
VOID
XhcClearOpRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data &= ~Bit;
@ -423,39 +417,74 @@ XhcClearOpRegBit (
Wait the operation register's bit as specified by Bit
to become set (or clear).
@param Xhc The XHCI Instance.
@param Offset The offset of the operation register.
@param Bit The bit of the register to wait for.
@param WaitToSet Wait the bit to set or clear.
@param Timeout The time to wait before abort (in millisecond, ms).
@param Xhc The XHCI Instance.
@param Offset The offset of the operation register.
@param Bit The bit of the register to wait for.
@param WaitToSet Wait the bit to set or clear.
@param Timeout The time to wait before abort (in millisecond, ms).
@retval EFI_SUCCESS The bit successfully changed by host controller.
@retval EFI_TIMEOUT The time out occurred.
@retval EFI_SUCCESS The bit successfully changed by host controller.
@retval EFI_TIMEOUT The time out occurred.
@retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated.
**/
EFI_STATUS
XhcWaitOpRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
)
{
UINT32 Index;
UINT64 Loop;
EFI_STATUS Status;
EFI_EVENT TimeoutEvent;
Loop = Timeout * XHC_1_MILLISECOND;
TimeoutEvent = NULL;
for (Index = 0; Index < Loop; Index++) {
if (Timeout == 0) {
return EFI_TIMEOUT;
}
Status = gBS->CreateEvent (
EVT_TIMER,
TPL_CALLBACK,
NULL,
NULL,
&TimeoutEvent
);
if (EFI_ERROR (Status)) {
goto DONE;
}
Status = gBS->SetTimer (
TimeoutEvent,
TimerRelative,
EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
);
if (EFI_ERROR (Status)) {
goto DONE;
}
do {
if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
return EFI_SUCCESS;
Status = EFI_SUCCESS;
goto DONE;
}
gBS->Stall (XHC_1_MICROSECOND);
} while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
Status = EFI_TIMEOUT;
DONE:
if (TimeoutEvent != NULL) {
gBS->CloseEvent (TimeoutEvent);
}
return EFI_TIMEOUT;
return Status;
}
/**
@ -466,16 +495,16 @@ XhcWaitOpRegBit (
**/
VOID
XhcSetBiosOwnership (
IN USB_XHCI_INSTANCE *Xhc
IN USB_XHCI_INSTANCE *Xhc
)
{
UINT32 Buffer;
UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
}
DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
DEBUG ((DEBUG_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
@ -490,16 +519,16 @@ XhcSetBiosOwnership (
**/
VOID
XhcClearBiosOwnership (
IN USB_XHCI_INSTANCE *Xhc
IN USB_XHCI_INSTANCE *Xhc
)
{
UINT32 Buffer;
UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
}
DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
DEBUG ((DEBUG_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
@ -517,13 +546,13 @@ XhcClearBiosOwnership (
**/
UINT32
XhcGetCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 CapId
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 CapId
)
{
UINT32 ExtCapOffset;
UINT8 NextExtCapReg;
UINT32 Data;
UINT32 ExtCapOffset;
UINT8 NextExtCapReg;
UINT32 Data;
ExtCapOffset = 0;
@ -535,6 +564,7 @@ XhcGetCapabilityAddr (
if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
//
// If not, then traverse all of the ext capability registers till finding out it.
//
@ -545,6 +575,184 @@ XhcGetCapabilityAddr (
return 0xFFFFFFFF;
}
/**
Calculate the offset of the xHCI Supported Protocol Capability.
@param Xhc The XHCI Instance.
@param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
@return The offset of xHCI Supported Protocol capability register.
**/
UINT32
XhcGetSupportedProtocolCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 MajorVersion
)
{
UINT32 ExtCapOffset;
UINT8 NextExtCapReg;
UINT32 Data;
UINT32 NameString;
XHC_SUPPORTED_PROTOCOL_DW0 UsbSupportDw0;
if (Xhc == NULL) {
return 0;
}
ExtCapOffset = 0;
do {
//
// Check if the extended capability register's capability id is USB Legacy Support.
//
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
UsbSupportDw0.Dword = Data;
if ((Data & 0xFF) == XHC_CAP_USB_SUPPORTED_PROTOCOL) {
if (UsbSupportDw0.Data.RevMajor == MajorVersion) {
NameString = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET);
if (NameString == XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE) {
//
// Ensure Name String field is xHCI supported protocols in xHCI Supported Protocol Capability Offset 04h
//
return ExtCapOffset;
}
}
}
//
// If not, then traverse all of the ext capability registers till finding out it.
//
NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);
ExtCapOffset += (NextExtCapReg << 2);
} while (NextExtCapReg != 0);
return 0xFFFFFFFF;
}
/**
Find PortSpeed value match Protocol Speed ID Value (PSIV).
@param Xhc The XHCI Instance.
@param ExtCapOffset The USB Major Version in xHCI Support Protocol Capability Field
@param PortSpeed The Port Speed Field in USB PortSc register
@return The Protocol Speed ID (PSI) from xHCI Supported Protocol capability register.
**/
UINT32
XhciPsivGetPsid (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 ExtCapOffset,
IN UINT8 PortSpeed
)
{
XHC_SUPPORTED_PROTOCOL_DW2 PortId;
XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Reg;
UINT32 Count;
if ((Xhc == NULL) || (ExtCapOffset == 0xFFFFFFFF)) {
return 0;
}
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2 xHCI Supported Protocol Capability
// 1. Get the PSIC(Protocol Speed ID Count) value.
// 2. The PSID register boundary should be Base address + PSIC * 0x04
//
PortId.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_DW2_OFFSET);
for (Count = 0; Count < PortId.Data.Psic; Count++) {
Reg.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_PSI_OFFSET + (Count << 2));
if (Reg.Data.Psiv == PortSpeed) {
return Reg.Dword;
}
}
return 0;
}
/**
Find PortSpeed value match case in XHCI Supported Protocol Capability
@param Xhc The XHCI Instance.
@param PortSpeed The Port Speed Field in USB PortSc register
@return The USB Port Speed.
**/
UINT16
XhcCheckUsbPortSpeedUsedPsic (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 PortSpeed
)
{
XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID SpField;
UINT16 UsbSpeedIdMap;
if (Xhc == NULL) {
return 0;
}
SpField.Dword = 0;
UsbSpeedIdMap = 0;
//
// Check xHCI Supported Protocol Capability, find the PSIV field to match
// PortSpeed definition when the Major Revision is 03h.
//
if (Xhc->Usb3SupOffset != 0xFFFFFFFF) {
SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed);
if (SpField.Dword != 0) {
//
// Found the corresponding PORTSC value in PSIV field of USB3 offset.
//
UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;
}
}
//
// Check xHCI Supported Protocol Capability, find the PSIV field to match
// PortSpeed definition when the Major Revision is 02h.
//
if ((UsbSpeedIdMap == 0) && (Xhc->Usb2SupOffset != 0xFFFFFFFF)) {
SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed);
if (SpField.Dword != 0) {
//
// Found the corresponding PORTSC value in PSIV field of USB2 offset.
//
if (SpField.Data.Psie == 2) {
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
// PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 2 shall represent bit rate in Mb/s
//
if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM) {
//
// PSIM shows as default High-speed protocol, apply to High-speed mapping
//
UsbSpeedIdMap = USB_PORT_STAT_HIGH_SPEED;
}
} else if (SpField.Data.Psie == 1) {
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
// PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 1 shall represent bit rate in Kb/s
//
if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM) {
//
// PSIM shows as default Low-speed protocol, apply to Low-speed mapping
//
UsbSpeedIdMap = USB_PORT_STAT_LOW_SPEED;
}
}
}
}
return UsbSpeedIdMap;
}
/**
Whether the XHCI host controller is halted.
@ -556,13 +764,12 @@ XhcGetCapabilityAddr (
**/
BOOLEAN
XhcIsHalt (
IN USB_XHCI_INSTANCE *Xhc
IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
}
/**
Whether system error occurred.
@ -574,7 +781,7 @@ XhcIsHalt (
**/
BOOLEAN
XhcIsSysError (
IN USB_XHCI_INSTANCE *Xhc
IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
@ -594,11 +801,11 @@ XhcSetHsee (
IN USB_XHCI_INSTANCE *Xhc
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT16 XhciCmd;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT16 XhciCmd;
PciIo = Xhc->PciIo;
PciIo = Xhc->PciIo;
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@ -606,7 +813,7 @@ XhcSetHsee (
sizeof (XhciCmd) / sizeof (UINT16),
&XhciCmd
);
if (!EFI_ERROR(Status)) {
if (!EFI_ERROR (Status)) {
if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);
}
@ -625,28 +832,29 @@ XhcSetHsee (
**/
EFI_STATUS
XhcResetHC (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = EFI_SUCCESS;
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
DEBUG ((DEBUG_INFO, "XhcResetHC!\n"));
//
// Host can only be reset when it is halt. If not so, halt it
//
if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
Status = XhcHaltHC (Xhc, Timeout);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
}
if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))
{
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
//
// Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
@ -656,7 +864,7 @@ XhcResetHC (
gBS->Stall (XHC_1_MILLISECOND);
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
if (!EFI_ERROR(Status)) {
if (!EFI_ERROR (Status)) {
//
// The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.
// Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
@ -668,7 +876,6 @@ XhcResetHC (
return Status;
}
/**
Halt the XHCI host controller.
@ -681,18 +888,17 @@ XhcResetHC (
**/
EFI_STATUS
XhcHaltHC (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
return Status;
}
/**
Set the XHCI host controller to run.
@ -705,14 +911,13 @@ XhcHaltHC (
**/
EFI_STATUS
XhcRunHC (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
return Status;
}

431
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
View File

@ -10,187 +10,246 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_XHCI_REG_H_
#define _EFI_XHCI_REG_H_
#define PCI_IF_XHCI 0x30
#define PCI_IF_XHCI 0x30
//
// PCI Configuration Registers
//
#define XHC_BAR_INDEX 0x00
#define XHC_BAR_INDEX 0x00
#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
#define USB_HUB_CLASS_CODE 0x09
#define USB_HUB_SUBCLASS_CODE 0x00
#define USB_HUB_CLASS_CODE 0x09
#define USB_HUB_SUBCLASS_CODE 0x00
#define XHC_CAP_USB_LEGACY 0x01
#define XHC_CAP_USB_DEBUG 0x0A
#define XHC_CAP_USB_LEGACY 0x01
#define XHC_CAP_USB_DEBUG 0x0A
#define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02
//============================================//
// ============================================//
// XHCI register offset //
//============================================//
// ============================================//
//
// Capability registers offset
//
#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
//
// Operational registers offset
//
#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
//
// Runtime registers offset
//
#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Debug registers offset
//
#define XHC_DC_DCCTRL 0x20
#define XHC_DC_DCCTRL 0x20
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
//
// xHCI Supported Protocol Capability
//
#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02
#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03
#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04
#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355
#define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08
#define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10
#define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480
#define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500
#pragma pack (1)
typedef struct {
UINT8 MaxSlots; // Number of Device Slots
UINT16 MaxIntrs:11; // Number of Interrupters
UINT16 Rsvd:5;
UINT8 MaxPorts; // Number of Ports
UINT8 MaxSlots; // Number of Device Slots
UINT16 MaxIntrs : 11; // Number of Interrupters
UINT16 Rsvd : 5;
UINT8 MaxPorts; // Number of Ports
} HCSPARAMS1;
//
// Structural Parameters 1 Register Bitmap Definition
//
typedef union {
UINT32 Dword;
HCSPARAMS1 Data;
UINT32 Dword;
HCSPARAMS1 Data;
} XHC_HCSPARAMS1;
typedef struct {
UINT32 Ist:4; // Isochronous Scheduling Threshold
UINT32 Erst:4; // Event Ring Segment Table Max
UINT32 Rsvd:13;
UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
UINT32 Spr:1; // Scratchpad Restore
UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
UINT32 Ist : 4; // Isochronous Scheduling Threshold
UINT32 Erst : 4; // Event Ring Segment Table Max
UINT32 Rsvd : 13;
UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
UINT32 Spr : 1; // Scratchpad Restore
UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
} HCSPARAMS2;
//
// Structural Parameters 2 Register Bitmap Definition
//
typedef union {
UINT32 Dword;
HCSPARAMS2 Data;
UINT32 Dword;
HCSPARAMS2 Data;
} XHC_HCSPARAMS2;
typedef struct {
UINT16 Ac64:1; // 64-bit Addressing Capability
UINT16 Bnc:1; // BW Negotiation Capability
UINT16 Csz:1; // Context Size
UINT16 Ppc:1; // Port Power Control
UINT16 Pind:1; // Port Indicators
UINT16 Lhrc:1; // Light HC Reset Capability
UINT16 Ltc:1; // Latency Tolerance Messaging Capability
UINT16 Nss:1; // No Secondary SID Support
UINT16 Pae:1; // Parse All Event Data
UINT16 Rsvd:3;
UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
UINT16 Ac64 : 1; // 64-bit Addressing Capability
UINT16 Bnc : 1; // BW Negotiation Capability
UINT16 Csz : 1; // Context Size
UINT16 Ppc : 1; // Port Power Control
UINT16 Pind : 1; // Port Indicators
UINT16 Lhrc : 1; // Light HC Reset Capability
UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
UINT16 Nss : 1; // No Secondary SID Support
UINT16 Pae : 1; // Parse All Event Data
UINT16 Rsvd : 3;
UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
} HCCPARAMS;
//
// Capability Parameters Register Bitmap Definition
//
typedef union {
UINT32 Dword;
HCCPARAMS Data;
UINT32 Dword;
HCCPARAMS Data;
} XHC_HCCPARAMS;
//
// xHCI Supported Protocol Cabability
//
typedef struct {
UINT8 CapId;
UINT8 NextExtCapReg;
UINT8 RevMinor;
UINT8 RevMajor;
} SUPPORTED_PROTOCOL_DW0;
typedef union {
UINT32 Dword;
SUPPORTED_PROTOCOL_DW0 Data;
} XHC_SUPPORTED_PROTOCOL_DW0;
typedef struct {
UINT32 NameString;
} XHC_SUPPORTED_PROTOCOL_DW1;
typedef struct {
UINT8 CompPortOffset;
UINT8 CompPortCount;
UINT16 ProtocolDef : 12;
UINT16 Psic : 4;
} SUPPORTED_PROTOCOL_DW2;
typedef union {
UINT32 Dword;
SUPPORTED_PROTOCOL_DW2 Data;
} XHC_SUPPORTED_PROTOCOL_DW2;
typedef struct {
UINT16 Psiv : 4;
UINT16 Psie : 2;
UINT16 Plt : 2;
UINT16 Pfd : 1;
UINT16 RsvdP : 5;
UINT16 Lp : 2;
UINT16 Psim;
} SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
typedef union {
UINT32 Dword;
SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data;
} XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
#pragma pack ()
//
// Register Bit Definition
//
#define XHC_USBCMD_RUN BIT0 // Run/Stop
#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
#define XHC_USBCMD_RUN BIT0 // Run/Stop
#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
#define XHC_USBSTS_HSE BIT2 // Host System Error
#define XHC_USBSTS_EINT BIT3 // Event Interrupt
#define XHC_USBSTS_PCD BIT4 // Port Change Detect
#define XHC_USBSTS_SSS BIT8 // Save State Status
#define XHC_USBSTS_RSS BIT9 // Restore State Status
#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
#define XHC_USBSTS_HCE BIT12 // Host Controller Error
#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
#define XHC_USBSTS_HSE BIT2 // Host System Error
#define XHC_USBSTS_EINT BIT3 // Event Interrupt
#define XHC_USBSTS_PCD BIT4 // Port Change Detect
#define XHC_USBSTS_SSS BIT8 // Save State Status
#define XHC_USBSTS_RSS BIT9 // Restore State Status
#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
#define XHC_USBSTS_HCE BIT12 // Host Controller Error
#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
#define XHC_CRCR_RCS BIT0 // Ring Cycle State
#define XHC_CRCR_CS BIT1 // Command Stop
#define XHC_CRCR_CA BIT2 // Command Abort
#define XHC_CRCR_CRR BIT3 // Command Ring Running
#define XHC_CRCR_RCS BIT0 // Ring Cycle State
#define XHC_CRCR_CS BIT1 // Command Stop
#define XHC_CRCR_CA BIT2 // Command Abort
#define XHC_CRCR_CRR BIT3 // Command Ring Running
#define XHC_CONFIG_MASK 0xFF // Command Ring Running
#define XHC_CONFIG_MASK 0xFF // Command Ring Running
#define XHC_PORTSC_CCS BIT0 // Current Connect Status
#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
#define XHC_PORTSC_OCA BIT3 // Over-current Active
#define XHC_PORTSC_RESET BIT4 // Port Reset
#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
#define XHC_PORTSC_PP BIT9 // Port Power
#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
#define XHC_PORTSC_CSC BIT17 // Connect Status Change
#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
#define XHC_PORTSC_OCC BIT20 // Over-Current Change
#define XHC_PORTSC_PRC BIT21 // Port Reset Change
#define XHC_PORTSC_PLC BIT22 // Port Link State Change
#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
#define XHC_PORTSC_CCS BIT0 // Current Connect Status
#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
#define XHC_PORTSC_OCA BIT3 // Over-current Active
#define XHC_PORTSC_RESET BIT4 // Port Reset
#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
#define XHC_PORTSC_PP BIT9 // Port Power
#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
#define XHC_PORTSC_CSC BIT17 // Connect Status Change
#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
#define XHC_PORTSC_OCC BIT20 // Over-Current Change
#define XHC_PORTSC_PRC BIT21 // Port Reset Change
#define XHC_PORTSC_PLC BIT22 // Port Link State Change
#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
#define XHC_IMAN_IP BIT0 // Interrupt Pending
#define XHC_IMAN_IE BIT1 // Interrupt Enable
#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
#define XHC_IMAN_IP BIT0 // Interrupt Pending
#define XHC_IMAN_IE BIT1 // Interrupt Enable
#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
//
// Hub Class Feature Selector for Clear Port Feature Request
@ -198,8 +257,8 @@ typedef union {
// For more details, Please refer to USB 3.0 Spec Table 10-7.
//
typedef enum {
Usb3PortBHPortReset = 28,
Usb3PortBHPortResetChange = 29
Usb3PortBHPortReset = 28,
Usb3PortBHPortResetChange = 29
} XHC_PORT_FEATURE;
//
@ -207,16 +266,16 @@ typedef enum {
// UEFI's port states.
//
typedef struct {
UINT32 HwState;
UINT16 UefiState;
UINT32 HwState;
UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
// Structure to map the hardware port states to feature selector for clear port feature request.
//
typedef struct {
UINT32 HwState;
UINT16 Selector;
UINT32 HwState;
UINT16 Selector;
} USB_CLEAR_PORT_MAP;
/**
@ -231,8 +290,8 @@ typedef struct {
**/
UINT8
XhcReadCapReg8 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
@ -247,8 +306,8 @@ XhcReadCapReg8 (
**/
UINT32
XhcReadCapReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
@ -263,8 +322,8 @@ XhcReadCapReg (
**/
UINT32
XhcReadOpReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
@ -277,12 +336,11 @@ XhcReadOpReg (
**/
VOID
XhcWriteOpReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
Read XHCI runtime register.
@ -294,8 +352,8 @@ XhcWriteOpReg (
**/
UINT32
XhcReadRuntimeReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
@ -308,12 +366,11 @@ XhcReadRuntimeReg (
**/
VOID
XhcWriteRuntimeReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
Write the data to the XHCI door bell register.
@ -324,9 +381,9 @@ XhcWriteRuntimeReg (
**/
VOID
XhcWriteDoorBellReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@ -339,9 +396,9 @@ XhcWriteDoorBellReg (
**/
VOID
XhcSetOpRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@ -354,9 +411,9 @@ XhcSetOpRegBit (
**/
VOID
XhcClearOpRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@ -375,11 +432,11 @@ XhcClearOpRegBit (
**/
EFI_STATUS
XhcWaitOpRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
);
/**
@ -393,8 +450,8 @@ XhcWaitOpRegBit (
**/
UINT32
XhcReadRuntimeReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
@ -407,9 +464,9 @@ XhcReadRuntimeReg (
**/
VOID
XhcWriteRuntimeReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@ -422,9 +479,9 @@ XhcWriteRuntimeReg (
**/
VOID
XhcSetRuntimeRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@ -437,9 +494,9 @@ XhcSetRuntimeRegBit (
**/
VOID
XhcClearRuntimeRegBit (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@ -453,8 +510,8 @@ XhcClearRuntimeRegBit (
**/
UINT32
XhcReadExtCapReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
@ -468,7 +525,7 @@ XhcReadExtCapReg (
**/
BOOLEAN
XhcIsHalt (
IN USB_XHCI_INSTANCE *Xhc
IN USB_XHCI_INSTANCE *Xhc
);
/**
@ -482,7 +539,7 @@ XhcIsHalt (
**/
BOOLEAN
XhcIsSysError (
IN USB_XHCI_INSTANCE *Xhc
IN USB_XHCI_INSTANCE *Xhc
);
/**
@ -497,8 +554,8 @@ XhcIsSysError (
**/
EFI_STATUS
XhcResetHC (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
);
/**
@ -513,8 +570,8 @@ XhcResetHC (
**/
EFI_STATUS
XhcHaltHC (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
);
/**
@ -529,8 +586,8 @@ XhcHaltHC (
**/
EFI_STATUS
XhcRunHC (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Timeout
);
/**
@ -544,8 +601,38 @@ XhcRunHC (
**/
UINT32
XhcGetCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 CapId
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 CapId
);
/**
Calculate the offset of the xHCI Supported Protocol Capability.
@param Xhc The XHCI Instance.
@param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
@return The offset of xHCI Supported Protocol capability register.
**/
UINT32
XhcGetSupportedProtocolCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 MajorVersion
);
/**
Find SpeedField value match with Port Speed ID value.
@param Xhc The XHCI Instance.
@param Speed The Port Speed filed in USB PortSc register
@return The USB Port Speed.
**/
UINT16
XhcCheckUsbPortSpeedUsedPsic (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 Speed
);
#endif

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MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
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